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Video Encoder with Six 10-Bit DACs, 54 MHz Oversampling and Progressive Scan Inputs ADV7192
APPLICATIONS DVD Playback Systems PC Video/Multimedia Playback Systems Progressive Scan Playback Systems GENERAL DESCRIPTION
FEATURES Six High-Quality 10-Bit Video DACs 10-Bit Internal Digital Video Processing Multistandard Video Input Multistandard Video Output 4 Oversampling with Internal 54 MHz PLL Programmable Video Control Includes: Digital Noise Reduction Gamma Correction Black Burst LUMA Delay CHROMA Delay Multiple Luma and Chroma Filters Luma SSAFTM (Super Subalias Filter) Average Brightness Detection Field Counter Macrovision Rev. 7.1 CGMS (Copy Generation Management System) WSS (Wide Screen Signaling) Closed Captioning Support. Teletext Insertion Port (PAL-WST) 2-Wire Serial MPU Interface (I2C(R)-Compatible and Fast I2C) 2 I C Interface Supply Voltage 5 V and 3.3 V Operation 80-Lead LQFP Package
The ADV7192 is part of the new generation of video encoders from Analog Devices. The device builds on the performance of previous video encoders and provides new features like interfacing progressive scan devices, Digital Noise Reduction, Gamma Correction, 4x Oversampling and 54 MHz operation, Average Brightness Detection, Black Burst Signal Generation, Chroma Delay, an additional Chroma Filter, and other features. The ADV7192 supports NTSC-M, NTSC-N (Japan), PAL N, PAL M, PAL-B/D/G/H/I and PAL-60 standards. Input standards supported include ITU-R.BT656 4:2:2 YCrCb in 8-Bit or 16-Bit format and 3x 10-Bit YCrCb progressive scan format. The ADV7192 can output Composite Video (CVBS), S-Video (Y/C), Component YUV or RGB and analog progressive scan in YPrPb format. The analog component output is also compatible with Betacam, MII, and SMPTE/EBU N10 levels, SMPTE 170 M NTSC, and ITU-R.BT 470 PAL. Please see Detailed Description of Features for more information about the ADV7192.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
DIGITAL INPUT VIDEO INPUT PROCESSING PLL AND 54MHz DEMUX ITU-R.BT 656/601 8-BIT YCrCb IN 4:2:2 FORMAT AND YCrCbTOYUV MATRIX COLOR CONTROL DNR GAMMA CORRECTION CHROMA LPF 2 OVERSAMPLING SSAF LPF 10-BIT DAC 10-BIT DAC 10-BIT DAC 10-BIT DAC 10-BIT DAC 10-BIT DAC I2C INTERFACE COMPOSITE VIDEO Y [S-VIDEO] C [S-VIDEO] RGB YUV YPrPb TV SCREEN OR PROGRESSIVE SCAN DISPLAY VIDEO SIGNAL PROCESSING VIDEO OUTPUT PROCESSING ANALOG OUTPUT
27MHz CLOCK
OR
VBI TELETEXT CLOSED CAPTION CGMS/WSS
LUMA LPF
4 OVERSAMPLING
ADV7192
SSAF is a trademark of Analog Devices Inc. This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations). I2C is a registered trademark of Philips Corporation. Throughout the document YUV refers to digital or analog component video.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
ADV7192
CONTENTS
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1 SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM . . . . . . 1 SPECIFICATIONS Static Performance 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Static Performance 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Dynamic Specifications 5 V . . . . . . . . . . . . . . . . . . . . . . . . 5 Dynamic Specifications 3.3 V . . . . . . . . . . . . . . . . . . . . . . . 5 Timing Characteristics 5 V . . . . . . . . . . . . . . . . . . . . . . . . 6 Timing Characteristics 3.3 V . . . . . . . . . . . . . . . . . . . . . . . 7 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 9 PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PACKAGE THERMAL PERFORMANCE . . . . . . . . . . . . . 9 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 10 DETAILED DESCRIPTION OF FEATURES . . . . . . . . . 11 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 11 DATA PATH DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 12 INTERNAL FILTER RESPONSE . . . . . . . . . . . . . . . . . . . 13 FEATURES: FUNCTIONAL DESCRIPTION . . . . . . . . . 17 BLACK BURST OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . 17 BRIGHTNESS DETECT . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CHROMA/LUMA DELAY . . . . . . . . . . . . . . . . . . . . . . . . 17 CLAMP OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CSO, HSO AND VSO OUTPUTS . . . . . . . . . . . . . . . . . . . 17 COLOR BAR GENERATION . . . . . . . . . . . . . . . . . . . . . . 17 COLOR BURST SIGNAL CONTROL . . . . . . . . . . . . . . . 17 COLOR CONTROLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 CHROMINANCE CONTROL . . . . . . . . . . . . . . . . . . . . . 17 UNDERSHOOT LIMITER . . . . . . . . . . . . . . . . . . . . . . . . 18 DIGITAL NOISE REDUCTION . . . . . . . . . . . . . . . . . . . . 18 DOUBLE BUFFERING . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 GAMMA CORRECTION CONTROL . . . . . . . . . . . . . . . 18 NTSC PEDESTAL CONTROL . . . . . . . . . . . . . . . . . . . . . 18 POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PROGRESSIVE SCAN INPUT . . . . . . . . . . . . . . . . . . . . . 18 REAL-TIME CONTROL, SUBCARRIER RESET, AND TIMING RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SCH PHASE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SLEEP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . . 19 VERTICAL BLANKING DATA INSERTION AND BLANK INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 YUV LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 16-BIT INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4x OVERSAMPLING AND INTERNAL PLL . . . . . . . . . 20 VIDEO TIMING DESCRIPTION . . . . . . . . . . . . . . . . . . . 20 RESET SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 28 REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 29 MODE REGISTERS 0-9 . . . . . . . . . . . . . . . . . . . . . . . 30-35 TIMING REGISTERS 0-17 . . . . . . . . . . . . . . . . . . . . . . . 36 SUBCARRIER FREQUENCY AND PHASE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CLOSED CAPTIONING REGISTERS . . . . . . . . . . . . . . . 37 NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 TELETEXT CONTROL REGISTER . . . . . . . . . . . . . . . . 38 CGMS_WSS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . 38 CONTRAST CONTROL REGISTERS . . . . . . . . . . . . . . . 39 HUE ADJUST CONTROL REGISTER (HCR) . . . . . . . . 40 HCR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 40 BRIGHTNESS CONTROL REGISTER (BCR) . . . . . . . . 40 BCR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 40 SHARPNESS RESPONSE REGISTER (PR) . . . . . . . . . . . 41 PR BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DNR REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DNR BIT DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 41 GAMMA CORRECTION REGISTERS . . . . . . . . . . . . . . 43 BRIGHTNESS DETECT REGISTER . . . . . . . . . . . . . . . . 44 OUTPUT CLOCK REGISTER . . . . . . . . . . . . . . . . . . . . . 44 OCR BIT DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . 44 APPENDIX 1 Board Design and Layout Considerations . . . . . . . . . . . . 45 APPENDIX 2 Closed Captioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 APPENDIX 3 Copy Generation Management System (CGMS) . . . . . . . 48 APPENDIX 4 Wide Screen Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 APPENDIX 5 Teletext Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 APPENDIX 6 Optional Output Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 APPENDIX 7 DAC Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 APPENDIX 8 Recommended Register Values . . . . . . . . . . . . . . . . . . . . 53 APPENDIX 9 NTSC Waveforms (With Pedestal) . . . . . . . . . . . . . . . . . 57 NTSC Waveforms (Without Pedestal) . . . . . . . . . . . . . . . 58 PAL Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Video Measurement Plots . . . . . . . . . . . . . . . . . . . . . . . . 60 UV Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Output Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 APPENDIX 10 Vector Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 69
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ADV7192
SPECIFICATIONS
5 V SPECIFICATIONS
Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity3 Differential Nonlinearity3 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN Input Leakage Current4 Input Leakage Current5 DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current6 Three-State Leakage Current7 Three-State Output Capacitance ANALOG OUTPUTS Output Current (Max) Output Current (Min) DAC-to-DAC Matching3 Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT VOLTAGE REFERENCE Reference Range, VREF8 POWER REQUIREMENTS VAA Normal Power Mode IDAC (Max)9 ICCT (2x Oversampling) 10, 11 ICCT (4x Oversampling)10, 11 IPLL Sleep Mode IDAC ICCT 2.0 0 6 1 200 2.4 0.8 10 200 6 4.125 4.33 2.16 0.4 0 100 6 1.112 4.75 1.235 5.0 29 80 120 6 0.01 85 1.359 5.25 35 120 170 10 0.4 0.8 1 10
1 (VAA = 5 V, VREF = 1.235 V, RSET1,2 = 1200
unless otherwise noted.)
Min Typ
unless otherwise noted. All specifications TMIN to TMAX2
Max 10 1.0 1.0 Unit Bits LSB LSB V V A pF A A V V A A pF mA mA % V k pF V V mA mA mA mA A A Test Conditions
Guaranteed Monotonic
VIN = 0.4 V or 2.4 V
ISOURCE = 400 A ISINK = 3.2 mA
10 4.625
RL = 300 RL = 600 RSET1, RSET2 = 2400
2.5 1.4
IOUT = 0 mA
NOTES 1 All measurements are made in 4x Oversampling Mode unless otherwise specified. 2 Temperature range T MIN to TMAX: 0C to 70C. 3 Guaranteed by characterization. 4 For all inputs but PAL_NTSC and ALSB. 5 For PAL_NTSC and ALSB inputs. 6 For all outputs but VSO/TTX/CLAMP. 7 For VSO/TTX/CLAMP output. 8 Measurement made in 2x Oversampling Mode. 9 IDAC is the total current required to supply all DACs including the V REF Circuitry. 10 All six DACs ON. 11 ICCT or the circuit current, is the continuous current required to drive the digital core without I PLL. Specifications subject to change without notice.
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ADV7192-SPECIFICATIONS 1.235 V, R (V = 3.3 V, V =
3.3 V SPECIFICATIONS
Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current3 Input Leakage Current4 Input Current, IIN Input Capacitance, CIN DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current5 Three-State Leakage Current6 Three-State Output Capacitance ANALOG OUTPUTS Output Current (Max) Output Current (Min) DAC-to-DAC Matching Output Compliance, VOC Output Impedance, ROUT Output Capacitance, COUT VOLTAGE REFERENCE Reference Range, VREF7 POWER REQUIREMENTS VAA Normal Power Mode IDAC (Max)8 ICCT (2x Oversampling)9, 10 ICCT (4x Oversampling)9, 10 IPLL Sleep Mode IDAC10 ICCT 3.15 4.125 2 0.8 1 200 6 2.4 0.4 10 200 6 4.33 2.16 0.4 100 6
1
AA
REF
SET1,2 = 1200
unless otherwise noted. All specifications TMIN to TMAX2
Unit Bits LSB LSB V V A A A pF V V A A pF mA mA % V k pF V Test Conditions
unless otherwise noted.)
Min Typ Max 10 1.0 1.0
Guaranteed Monotonic
1 10
VIN = 0.4 V or 2.4 V
ISOURCE = 400 A ISINK = 3.2 mA
10 4.625 2.5 1.4
RL = 300 RL = 600 , RSET1,2 = 2400
IOUT = 0 mA IVREFOUT = 20 A
1.235 3.3 29 42 68 6 0.01 85 3.6
V mA mA mA mA A A
54 86
NOTES 1 All measurements are made in 4x Oversampling Mode unless otherwise specified and are guaranteed by characterization. In 2 x Oversampling Mode, power requirement for the ADV7192 is typically 3.0 V. 2 Temperature range T MIN to TMAX: 0C to 70C. 3 For all inputs but PAL_NTSC and ALSB. 4 For PAL_NTSC and ALSB inputs. 5 For all outputs but VSO/TTX/CLAMP. 6 For VSO/TTX/CLAMP output. 7 Measurement made in 2x Oversampling Mode. 8 IDAC is the total current required to supply all DACs including the V REF Circuitry. 9 All six DACs ON. 10 ICCT or the circuit current, is the continuous current required to drive the digital core without I PLL. Specifications subject to change without notice.
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ADV7192 5 V DYNAMIC-SPECIFICATIONS
Parameter Hue Accuracy Color Saturation Accuracy Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermod Chroma/Luma Gain Ineq Chroma/Luma Delay Ineq Luminance Nonlinearity Chroma AM Noise Chroma PM Noise Differential Gain3 Differential Phase3 SNR (Pedestal)3 SNR (Ramp)3 Min
1 (VAA = 5 V 250 mV, VREF2 = 1.235 V, RSET1,2 = 1200 specifications TMIN to TMAX unless otherwise noted.)
Typ 0.5 0.7 0.7 0.5 0.1 1.7 2.2 0.6 82 72 0.1 0.4 78.5 78 61.7 62 Max Unit Degrees % % Degrees % % ns % dB dB % Degrees dB rms dB p-p dB rms dB p-p
unless otherwise noted. All
Test Conditions
0.9
Referenced to 40 IRE
0.7
(0.4) (0.15) (78) (78) (61.7) (63)
0.3 (0.5) 0.5 (0.3)
RMS Peak Periodic RMS Peak Periodic
NOTES 1 All measurements are made in 4x Oversampling Mode unless otherwise specified and are guaranteed by characterization. 2 Temperature range T MIN to TMAX: 0C to 70C. 3 Values in parentheses apply to 2x Oversampling Mode. Specifications subject to change without notice.
3.3 V DYNAMIC-SPECIFICATIONS1 specifications T
Parameter Hue Accuracy Color Saturation Accuracy Luminance Nonlinearity Chroma AM Noise Chroma PM Noise Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermod Differential Gain3 Differential Phase3 SNR (Pedestal)3 SNR (Ramp)3 Min Typ 0.5 0.8 0.6 83 71 0.7 0.5 0.1 0.2 0.5 78.5 78 62.3 61
(VAA = 3.3 V
150 mV, VREF = 1.235 V, RSET1,2 = 1200 2 MIN to TMAX unless otherwise noted.)
Max Unit Degrees % % dB dB % Degrees % % Degrees dB rms dB p-p dB rms dB p-p
unless otherwise noted. All
Test Conditions
Referenced to 40 IRE
(0.5) (0.2) (78) (78) (62) (62.5)
RMS Peak Periodic RMS Peak Periodic
NOTES 1 All measurements are made in 4x Oversampling Mode unless otherwise specified and are guaranteed by characterization. 2 Temperature range T MIN to TMAX: 0C to 70C. 3 Values in parentheses apply to 2x Oversampling Mode. Specifications subject to change without notice.
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ADV7192 5 V TIMING CHARACTERISTICS
Parameter MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 ANALOG OUTPUTS Analog Output Delay DAC Analog Output Skew CLOCK CONTROL AND PIXEL PORT3 fCLOCK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t12 Control Setup Time, t11 Control Hold Time, t12 Digital Output Access Time, t13 Digital Output Hold Time, t14 Pipeline Delay, t15 (2x Oversampling) Pipeline Delay, t15 (4x Oversampling) TELETEXT PORT4 Digital Output Access Time, t16 Data Setup Time, t17 Data Hold Time, t18 RESET CONTROL RESET Low Time PLL PLL Output Frequency
NOTES 1 Temperature range T MIN to TMAX: 0C to 70C. 2 Guaranteed by characterization. 3 Pixel Port consists of: Data: P7-P0, Y0/P8-Y7/P15 Pixel Inputs Control: HSYNC, VSYNC, BLANK Clock: CLKIN 4 Teletext Port consists of: Digital Output: TTXRQ Data: TTX Specifications subject to change without notice.
2 2 2
(VAA = 5 V 250 mV, VREF = 1.235 V, RSET1,2 = 1200 V unless otherwise noted. All specifications TMIN to TMAX1 unless otherwise noted.)
Typ Max 400 Unit kHz s s s s ns ns ns s ns ns Test Conditions
Min 0 0.6 1.3 0.6 0.6 100
After This Period the First Clock Is Generated Relevant for Repeated Start Condition
300 300 0.6 8 0.1
8 8 6 5 6 4
27 2 3 2.5 2.0
13 12 57 67 11 3 6 3 54 20
MHz ns ns ns ns ns ns ns ns Clock Cycles Clock Cycles ns ns ns ns MHz
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ADV7192 3.3 V TIMING CHARACTERISTICS specifications T
Parameter MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 ANALOG OUTPUTS Analog Output Delay DAC Analog Output Skew CLOCK CONTROL AND PIXEL PORT 3 fCLOCK Clock High Time, t9 Clock Low Time, t10 Data Setup Time, t11 Data Hold Time, t12 Control Setup Time, t11 Control Hold Time, t12 Digital Output Access Time, t13 Digital Output Hold Time, t14 Pipeline Delay, t15 (2x Oversampling) TELETEXT PORT4 Digital Output Access Time, t16 Data Setup Time, t17 Data Hold Time, t18 RESET CONTROL RESET Low Time PLL PLL Output Frequency
NOTES 1 Temperature range T MIN to TMAX: 0C to 70C. 2 Guaranteed by characterization. 3 Pixel Port consists of: Data: P7-P0, Y0/P8-Y7/P15 Pixel Inputs Control: HSYNC, VSYNC, BLANK Clock: CLKIN 4 Teletext Port consists of: Digital Output: TTXRQ Data: TTX Specifications subject to change without notice.
(VAA = 3.3 V
Typ
150 mV, VREF = 1.235 V, RSET1,2 = 1200 1 2 MIN to TMAX unless otherwise noted.)
Unit kHz s s s s ns ns ns s ns ns
unless otherwise noted. All
Min 0 0.6 1.3 0.6 0.6 100
Max 400
Test Conditions
After This Period the First Clock Is Generated Relevant for Repeated Start Condition
300 300 0.6 2 8 0.1
8 8 6 4 2, 5 3
27 2 3 4 2.0
13 12 37 11 3 6 3 54 20
MHz ns ns ns ns ns ns ns ns Clock Cycles ns ns ns ns MHz
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ADV7192
t5 t3
SDA
t3
t6 t1
SCL
t2
t7
t4
t8
Figure 1. MPU Port Timing Diagram
CLOCK
t9
CONTROL I/PS HSYNC, VSYNC, BLANK Cb
t10
t12
PIXEL INPUT DATA HSYNC, VSYNC, BLANK, CSO_HSO, VSO, CLAMP
Y
Cr
Y
Cb
Y
t11
t13
CONTROL O/PS
t14
Figure 2. Pixel and Control Data Timing Diagram
TXTREQ
t16
CLOCK
t17
TXT
t18
4 CLOCK CYCLES
4 CLOCK CYCLES
4 CLOCK CYCLES
3 CLOCK CYCLES
4 CLOCK CYCLES
Figure 3. Teletext Timing Diagram
CLOCK
PROGRESSIVE SCAN INPUT
Y0-Y9 INCLUDING SYNC INFORMATION Cb0-Cb9
t9
Y0 Cb0
t 10
Y1 Cb1
t 12
Y2 Cb2 Y3 Cb3 Y4 Cb4 Y5 Cb5
Cr0-Cr9
Cr0
Cr1
Cr2
Cr3
Cr4
Cr5
t 11
Figure 4. Progressive Scan Input Timing
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ADV7192
ABSOLUTE MAXIMUM RATINGS 1 PACKAGE THERMAL PERFORMANCE
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage on any Digital Input Pin . . GND - 0.5 V to VAA + 0.5 V Storage Temperature (TS) . . . . . . . . . . . . . . -65C to +150C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . 150C Body Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 220C Analog Outputs to GND2 . . . . . . . . . . . . GND - 0.5 V to VAA
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration.
The 80-lead package is used for this device. The junction-toambient (JA) thermal resistance in still air on a four-layer PCB is 24.7C. To reduce power consumption when using this part the user can run the part on a 3.3 V supply, turn off any unused DACs. The user must at all times stay below the maximum junction temperature of 110C. The following equation shows how to calculate this junction temperature: Junction Temperature = (VAA x (IDAC + ICCT)) x JA + 70C TAMB IDAC = 10 mA + (sum of the average currents consumed by each powered-on DAC) Average current consumed by each powered-on DAC = (VREF x K )/RSET VREF = 1.235 V K = 4.2146
PIN CONFIGURATION
VSO/ TTX/CLAMP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
NC 1 NC 2 P0 3 P1 4 P2 5 P3 6 P4 7 P5 8 P6 9 P7 10 Y[0]/P8 11 Y[1]/P9 12 Y[2]/P10 13 Y[3]/P11 14 Y[4]/P12 15 Y[5]/P13 16 Y[6]/P14 17 Y[7]/P15 18 Y[8] 19 Y[9] 20
CSO_HSO
60 RESET 59 PAL_NTSC 58 RSET1 57 V REF 56 COMP 1 55 DAC A 54 DAC B 53 VAA 52 AGND 51 DAC C 50 DAC D 49 AGND 48 VAA 47 DAC E 46 DAC F 45 COMP 2 44 RSET2 43 DGND 42 ALSB 41 SCRESET/RTC/TR
DGND
DGND VDD Cr[4]
VDD Cb[3]
Cb[2] Cb[1]
Cb[0] Cr[9]
Cr[8] Cr[7]
Cr[6]
Cr[5]
Cr[3] Cr[2] Cr[1] AGND
PIN 1 IDENTIFIER
ADV7192 LQFP
TOP VIEW (Not to Scale)
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Cr[0]
NC = NO CONNECT
ORDERING GUIDE
Model ADV7192KST
Temperature Range 0C to 70C
Package Description 80-Lead Quad Flatpack
CLKIN CLKOUT VAA
TTXREQ
VSYNC BLANK Cb[4]
HSYNC
DGND
DGND VDD
Cb[5]
Cb[6]
Cb[7]
Cb[8]
Cb[9]
SCL SDA
VDD
Package Option ST-80
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7192 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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-9-
ADV7192
PIN FUNCTION DESCRIPTIONS Pin No. 1, 2 3-10 11-18 19, 20 21, 34, 68, 79 22, 33, 43, 69, 80 23 24 25 26-31, 75-78 32 35, 49, 52 36 Mnemonic NC P0-P7 Y0/P8-Y7/P15 Y8-Y9 VDD DGND HSYNC VSYNC BLANK Input/ Output I I Function No Connect. 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port. The LSB of the input data is set up on Pin P0 (Pin Number 3). 16-Bit 4:2:2 Multiplexed YCrCb Pixel Port (Bits 8-15). 1 x 10-bit progressive scan input for Ydata (Bits 0-7). 1 x 10-bit progressive scan input is Ydata (Bits 8 and 9). Digital Power Supply (3.3 V to 5 V). Digital Ground. HSYNC (Modes 1, 2, and 3) Control Signal. This pin may be configured to be an output (Master Mode) or an input (Slave Mode) and accept Sync Signals. VSYNC Control Signal. This pin may be configured as an output (Master Mode) or as an input (Slave Mode) and accept VSYNC as a Control Signal. Video Blanking Control Signal. This signal is optional. For further information see Vertical Blanking and Data Insertion Blanking Input section. 1 x 10-Bit Progressive Scan Input Port for Cb data. Teletext Data Request Output Signal, used to control teletext data transfer. Analog Ground. TTL Clock Input. Requires a stable 27 MHz reference clock for standard operation. Alternatively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be used for square pixel operation. Clock Output pin. Analog Power Supply (3.3 V to 5 V). MPU Port Serial Interface Clock Input. MPU Port Serial Data Input/Output. Multifunctional Input: Real Time Control (RTC) input, Timing Reset input, Subcarrier Reset input. TTL Address Input. This signal sets up the LSB of the MPU address. A 1200 resistor connected from this pin to GND is used to control full-scale amplitudes of the Video Signals from the DAC D, E, F. Compensation Pin for DACs D, E, and F. Connect a 0.1 F Capacitor from COMP2 to VAA. S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output. S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output. Composite/Y (progressive scan)/Y/Green Analog Output. This DAC is capable of providing 4.33 mA output. S-Video C/Pr/V/RED Analog Output. This DAC is capable of providing 4.33 mA output. S-Video Y/Pb/U/BLUE Analog Output. This DAC is capable of providing 4.33 mA output. Composite/Y(progressive scan)/Y/Green Analog Output. This DAC is capable of providing 4.33 mA output. Compensation Pin for DACs A, B, and C. Connect a 0.1 F Capacitor from COMP1 to VAA. Voltage Reference Input for DACs or Voltage Reference Output (1.235 V). An external VREF cannot be used in 4x Oversampling Mode. A 1200 resistor connected from this pin to GND is used to control full-scale amplitudes of the Video Signals from the DAC A, B, C. Input signal to select PAL or NTSC mode of operation, pin set to Logic 1 selects PAL. The input resets the on-chip timing generator and sets the ADV7192 into default mode. See Appendix 8 for Default Register settings. Dual function CSO or HSO Output Sync Signal at TTL Level. Multifunctional Pin. VSO Output Sync Signal at TTL level. Teletext Data Input pin. CLAMP TTL output signals can be used to drive external circuitry to enable clamping of all video signals. 1 x 10-Bit progressive scan input port for Cr data.
P G I/O I/O I/O
Cb4-Cb9, Cb0-Cb3 I TTXREQ O AGND G CLKIN I
37 38, 48, 53 39 40 41 42 44 45 46 47 50 51 54 55 56 57 58 59 60 61 62
CLKOUT VAA SCL SDA SCRESET/ RTC/TR ALSB RSET2 COMP 2 DAC F DAC E DAC D DAC C DAC B DAC A COMP 1 VREF RSET1 PAL_NTSC RESET CSO_HSO VSO/TTX/CLAMP
O P I I/O I I I O O O O O O O O I/O I I I O I/O
63-67, 70-74
Cr0-Cr4, Cr5-Cr9
I
-10-
REV. 0
ADV7192
DETAILED DESCRIPTION OF FEATURES Clocking: Single 27 MHz Clock Required to Run the Device 4 Oversampling with Internal 54 MHz PLL Square Pixel Operation Advanced Power Management Programmable Video Control Features: Digital Noise Reduction Black Burst Signal Generation Pedestal Level Hue, Brightness, Contrast, and Saturation Clamping Output Signal VBI (Vertical Blanking Interval) Subcarrier Frequency and Phase LUMA Delay CHROMA Delay Gamma Correction Luma And Chroma Filters Luma SSAF (Super Subalias Filter) Average Brightness Detection Field Counter Interlaced/Noninterlaced Operation Complete On-Chip Video Timing Generator Programmable Multimode Master/Slave Operation Macrovision Rev 7.1 CGMS (Copy Generation Management System) WSS (Wide Screen Signaling) Closed Captioning Support Teletext Insertion Port (PAL-WST) 2-Wire Serial MPU Interface (I2C-Compatible And Fast I 2C) I2C Registers Synchronized to VSYNC GENERAL DESCRIPTION
to input video data in 3 10-bit YCrCb progressive scan format to facilitate interfacing devices such as progressive scan systems. Six DACs are available on the ADV7192, each of which is capable of providing 4.33 mA of current. In addition to the composite output signal there is the facility to output S-Video (Y/C Video), RGB Video and YUV Video. All YUV formats (SMPTRE/EBU N10, MII or Betacam) are supported. The on-board SSAF (Super Subalias Filter) with extended luminance frequency response and sharp stopband attenuation enables studio quality video playback on modern TVs, giving optimal horizontal line resolution. An additional sharpness control feature allows high-frequency enhancement on the luminance signal.
DNR MODE
DNR CONTROL GAIN BLOCK SIZE CONTROL CORING GAIN DATA BORDER AREA CORING GAIN BORDER BLOCK OFFSET NOISE SIGNAL PATH INPUT FILTER BLOCK Y DATA INPUT FILTER OUTPUT THRESHOLD MAIN SIGNAL PATH SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL
DNR OUT
DNR SHARPNESS MODE
DNR CONTROL GAIN BLOCK SIZE CONTROL CORING GAIN DATA BORDER AREA CORING GAIN BORDER BLOCK OFFSET NOISE SIGNAL PATH INPUT FILTER BLOCK Y DATA INPUT FILTER OUTPUT >THRESHOLD? FILTER OUTPUT< THRESHOLD MAIN SIGNAL PATH ADD SIGNAL ABOVE THRESHOLD RANGE TO ORIGINAL SIGNAL
The ADV7192 is an integrated Digital Video Encoder that converts digital CCIR-601/656 4:2:2 8-bit or 16-bit component video data into a standard analog baseband television signal compatible with worldwide standards. Additionally, it is possible
PAL_NTSC HSYNC VSYNC BLANK RESET TTX TTXRQ
10
DNR OUT
Figure 6. Block Diagram for DNR Mode and DNR Sharpness Mode
SDA ALSB Cr0-Cr9 Cb0-Cb9 Y0-Y9
VSO/CLAMP
CSO_HSO CGMS/WSS AND CLOSED CAPTIONING CONTROL
SCL
VIDEO TIMING GENERATOR
I2C MPU PORT YUV-TO-RGB MATRIX AND YUV LEVEL CONTROL BLOCK
TELETEXT INSERTION BLOCK
10
YCrCb- Y TO10 YUV U MATRIX 10
V 10 10 10
DNR Y AND 10 GAMMA U CORRECTION 10
V
BRIGHTNESS CONTROL AND ADD SYNC AND INTERPOLATOR SATURATION CONTROL AND ADD BURST AND INTERPOLATOR
PROGRAMMABLE LUMA FILTER AND SHARPNESS FILTER
M U L T I P L E X E R
PROGRAMMABLE CHROMA FILTER
MODULATOR AND HUE CONTROL
P0 DEMUX P15
I N T E R P O L A T O R
I N T E R P O L A T O R
10-BIT DAC 10-BIT DAC 10-BIT DAC DAC CONTROL BLOCK 10-BIT DAC 10-BIT DAC 10-BIT DAC DAC CONTROL BLOCK
DAC A
DAC B
DAC C VREF RSET2 COMP2 DAC D
DAC F
DAC E
CLKIN CLKOUT
PLL
ADV7192
REAL-TIME CONTROL CIRCUIT
SIN/COS DDS BLOCK
RSET1 COMP1
SCRESET/RTC/TR
Figure 5. Detailed Functional Block Diagram
REV. 0
-11-
ADV7192
Digital Noise Reduction allows improved picture quality in removing low amplitude, high frequency noise. Figure 6 shows the DNR functionality in the two modes available. Programmable gamma correction is also available. The figure below shows the response of different gamma values to a ramp signal.
300 GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT FOR VARIOUS GAMMA VALUES
GAMMA-CORRECTED AMPLITUDE
The Output Video Frames are synchronized with the incoming data Timing Reference Codes. Optionally, the Encoder accepts (and can generate) HSYNC, VSYNC, and FIELD timing signals. These timing signals can be adjusted to change pulsewidth and position while the part is in master mode. HSO/CSO and VSO TTL outputs are also available and are timed to the analog output video. A separate teletext port enables the user to directly input teletext data during the vertical blanking interval. The ADV7192 also incorporates WSS and CGMS-A data control generation.
250 SIGNAL OUTPUTS 200 0.3 0.5 150
T PU IN 1.5
100
The ADV7192 modes are set up over a 2-wire serial bidirectional port (I2C-compatible) with two slave addresses, and the device is register-compatible with the ADV7172.
1.8
AL GN SI
The ADV7192 is packaged in an 80-lead LQFP package.
DATA PATH DESCRIPTION
50
0
0
50
100
150 LOCATION
200
250
Figure 7. Signal Input (Ramp) and Selectable Gamma Output Curves
The device is driven by a 27 MHz clock. Data can be output at 27 MHz or 54 MHz (on-board PLL) when 4 oversampling is enabled. Also, the output filter requirements in 4 oversampling and 2 oversampling differ, as can be seen in Figure 8.
0dB 2 FILTER REQUIREMENTS 4 FILTER REQUIREMENTS
For PAL B, D, G, H, I, M, N, and NTSCM, N modes, YCrCb 4:2:2 data is input via the CCIR-656/601-compatible Pixel Port at a 27 MHz Data Rate. The Pixel Data is demultiplexed to form three data paths. Y typically has a range of 16 to 235, Cr and Cb typically have a range of 128 112; however, it is possible to input data from 1 to 254 on both Y, Cb, and Cr. The ADV7192 supports PAL (B, D, G, H, I, N, M) and NTSCM, N (with and without Pedestal) and PAL60 standards. Digital noise reduction can be applied to the Y signal. Programmable gamma correction can also be applied to the Y signal if required. The Y data can be manipulated for contrast control and a setup level can be added for brightness control. The Cr, Cb data can be scaled to achieve color saturation control. All settings become effective at the start of the next field when double buffering is enabled.
-30dB 6.75MHz 13.5MHz 27.0MHz 40.5MHz 54.0MHz
Figure 8. Output Filter Requirements in 4x Oversampling Mode
ADV7192
2 6 I N T E R P O L A T I O N D A C O U T P U T S 54MHz OUTPUT RATE
The appropriate sync, blank, and burst levels are added to the YCrCb data. Macrovision antitaping, closed-captioning and teletext levels are also added to Y and the resultant data is interpolated to 54 MHz (4 Oversampling Mode). The interpolated data is filtered and scaled by three digital FIR filters. The U and V signals are modulated by the appropriate Subcarrier Sine/Cosine waveforms and a phase offset may be added onto the color subcarrier during active video to allow hue adjustment. The resulting U and V signals are added together to make up the Chrominance signal. The Luma (Y) signal can be delayed by up to six clock cycles (at 27 MHz) and the Chroma signal can be delayed by up to eight clock cycles (at 27 MHz). The Luma and Chroma signals are added together to make up the Composite Video Signal. All timing signals are controlled. The YCrCb data is also used to generate RGB data with appropriate sync and blank levels. The YUV levels are scaled to output the suitable SMPTE/EBU N10, MII, or Betacam levels. Each DAC can be individually powered off if not required. A complete description of DAC output configurations is given in the Mode Register 2 section. Video output levels are illustrated in Appendix 9.
MPEG2
PIXEL BUS 27MHz
ENCODER CORE
54MHz PLL
Figure 9. PLL and 4x Oversampling Block Diagram
The ADV7192 also supports both PAL and NTSC square pixel operation. In this case the encoder requires a 24.5454 MHz Clock for NTSC or 29.5 MHz Clock for PAL square pixel mode operation. All internal timing is generated on-chip. An advanced power management circuit enables optimal control of power consumption in normal operating modes or sleep modes.
-12-
REV. 0
ADV7192
When used to interface progressive scan systems, the ADV7192 allows input to YCrCb signals in Progressive Scan format (3 10-bit) before these signals are routed to the interpolation filters and the DACs.
INTERNAL FILTER RESPONSE
several different frequency responses including five low-pass responses, a CIF response, and a QCIF response, as can be seen in the following figures. All filter plots show the 4 Oversampling responses. In Extended Mode there is the option of 12 responses in the range from -4 dB to +4 dB. The desired response can be chosen by the user by programming the correct value via the I2C. The variation of frequency responses can be seen in the Tables I and II. For more detailed filter plots refer to Analog Devices' Application Note AN-562.
The Y Filter supports several different frequency responses including two low-pass responses, two notch responses, an Extended (SSAF) response with or without gain boost/attenuation, a CIF response, and a QCIF response. The UV/filter supports
Table I. Luminance Internal Filter Specifications (4
Oversampling)
Filter Type Low-Pass (NTSC) Low-Pass (PAL) Notch (NTSC) Notch (PAL) Extended (SSAF) CIF QCIF
Filter Selection MR04 0 0 0 0 1 1 1 MR03 0 0 1 1 0 0 1 MR02 0 1 0 1 0 1 0
Passband Ripple1 (dB) 0.16 0.1 0.09 0.1 0.04 0.127 Monotonic
3 dB Bandwidth2 (MHz) 4.24 4.81 2.3/4.9/6.6 3.1/5.6/6.4 6.45 3.02 1.5
Stopband Cutoff 3 (MHz) 6.05 6.41 8.03 8.02 8.03 5.04 3.74
Stopband Attentuation4 (dB) -75.2 -64.6 -87.3 -79.7 -86.6 -62.6 -88.2
NOTES 1 Passband Ripple is defined as the fluctuations from the 0 dB response in the passband, measured in (dB). The passband is defined to have 0-fc frequency limits for a low-pass filter, 0-f1 and f2-infinity for a notch filter, where fc, f1, f2 are the -3 dB points. 2 3 dB bandwidth refers to the -3 dB cutoff frequency. 3 Stopband Cutoff refers to the frequency at the attenuation point referred to under Note 4. 4 Stopband Attenuation refers to the attenuation point (dB) at the frequency referred to under Note 3.
Table II. Chrominance Internal Filter Specifications (4
Oversampling)
2
Filter Type 1.3 MHz Low-Pass 0.65 MHz Low-Pass 1.0 MHz Low-Pass 2.0 MHz Low-Pass 3.0 MHz Low-Pass CIF QCIF
Filter Selection MR07 0 0 0 0 1 1 1 MR06 0 0 1 1 0 0 1 MR05 0 1 0 1 0 1 0
Passband Ripple1 (dB) 0.09 Monotonic Monotonic 0.048 Monotonic Monotonic Monotonic
3 dB Bandwidth (MHz) 1.395 0.65 1.0 2.2 3.2 0.65 0.5
Stopband Cutoff 3 (MHz) 2.46 2.41 1.89 3.1 5.3 2.41 1.75
Stopband Attentuation4 (dB) -83.9 -71.1 -64.43 -65.9 -84.5 -71.1 -33.1
NOTES 1 Passband Ripple is defined as the fluctuations from the 0 dB response in the passband, measured in (dB). The passband is defined to have 0-fc frequency limits for a low-pass filter, 0-f1 and f2-infinity for a notch filter, where fc, f1, f2 are the -3 dB points. 2 3 dB bandwidth refers to the -3 dB cutoff frequency. 3 Stopband Cutoff refers to the frequency at the attenuation point referred to under Note 4. 4 Stopband Attenuation refers to the attenuation point (dB) at the frequency referred to under Note 3.
REV. 0
-13-
ADV7192
0 -10
0 -10
MAGNITUDE - dB
MAGNITUDE - dB
-20 -30 -40 -50 -60 -70
-20 -30 -40 -50 -60 -70
0
2
4
6 8 FREQUENCY - MHz
10
12
0
2
4
6 8 FREQUENCY - MHz
10
12
Figure 10. NTSC Low-Pass Luma Filter
Figure 13. PAL Notch Luma Filter
0 -10
0 -10
MAGNITUDE - dB
-30 -40 -50 -60 -70
MAGNITUDE - dB
-20
-20 -30 -40 -50 -60 -70
0
2
4
6 8 FREQUENCY - MHz
10
12
0
2
4
6 8 FREQUENCY - MHz
10
12
Figure 11. PAL Low-Pass Luma Filter
Figure 14. Extended Mode (SSAF) Luma Filter
0 -10
4 2 0
MAGNITUDE - dB
0 2 4 6 8 FREQUENCY - MHz 10 12
MAGNITUDE - dB
-20 -30 -40 -50 -60 -70
-2 -4 -6 -8 -10 -12
0
1
2
4 3 FREQUENCY - MHz
5
6
7
Figure 12. NTSC Notch Luma Filter
Figure 15. Extended SSAF Luma Filter and Programmable Gain/Attenuation Showing +4 dB/-12 dB Range
-14-
REV. 0
ADV7192
1
0
0
-10
MAGNITUDE - dB
MAGNITUDE - dB
-1
-20 -30 -40 -50
-2
-3
-4
-60 -70
-5
0
1
2
4 3 FREQUENCY - MHz
5
6
7
0
2
4
6 8 FREQUENCY - MHz
10
12
Figure 16. Extended SSAF and Programmable Attenuation, Showing Range 0 dB/-4 dB
Figure 19. Luma QCIF Filter
5
0
4
-10
MAGNITUDE - dB
MAGNITUDE - dB
3
-20 -30 -40 -50
2
1
0
-60 -70
-1
0
1
2
4 3 FREQUENCY - MHz
5
6
7
0
2
4
6 8 FREQUENCY - MHz
10
12
Figure 17. Extended SSAF and Programmable Gain, Showing Range 0 dB/+4 dB
Figure 20. Chroma 0.65 MHz Low-Pass Filter
0 -10
0 -10
MAGNITUDE - dB
MAGNITUDE - dB
0
-20 -30 -40 -50 -60 -70
-20 -30 -40 -50 -60 -70
2
4
6 8 FREQUENCY - MHz
10
12
0
2
4
6 8 FREQUENCY - MHz
10
12
Figure 18. Luma CIF Filter
Figure 21. Chroma 1.0 MHz Low-Pass Filter
REV. 0
-15-
ADV7192
0 -10 0 -10
MAGNITUDE - dB
-30 -40 -50 -60 -70
MAGNITUDE - dB
0 2 4 6 8 FREQUENCY - MHz 10 12
-20
-20 -30 -40 -50 -60 -70
0
2
4
6 8 FREQUENCY - MHz
10
12
Figure 22. Chroma 1.3 MHz Low-Pass Filter
Figure 25. Chroma CIF Filter
0 -10
0 -10
MAGNITUDE - dB
-30 -40 -50 -60 -70
MAGNITUDE - dB
0 2 4 6 8 FREQUENCY - MHz 10 12
-20
-20 -30 -40 -50 -60 -70
0
2
4
6 8 FREQUENCY - MHz
10
12
Figure 23. Chroma 2 MHz Low-Pass Filter
Figure 26. Chroma QCIF Filter
0 -10
MAGNITUDE - dB
-20 -30 -40 -50 -60 -70
0
2
4
6 8 FREQUENCY - MHz
10
12
Figure 24. Chroma 3 MHz Low-Pass Filter
-16-
REV. 0
ADV7192
FEATURES: FUNCTIONAL DESCRIPTION
BLACK BURST OUTPUT CSO, HSO AND VSO OUTPUTS
It is possible to output a black burst signal from two DACs. This signal output is very useful for professional video equipment since it enables two video sources to be locked together. (Mode Register 9.)
DIGITAL DATA GENERATOR
The ADV7192 supports three output timing signals, CSO (composite sync signal), HSO (Horizontal Sync Signal) and VSO (Vertical Sync Signal). These output TTL signals are aligned with the analog video outputs. See Figure 31 for an example of these waveforms. (Mode Register 7.)
EXAMPLE:- NTSC
ADV7192
CVBS
525
1
2
3
4
5
6
7
8
9
10
11-19
OUTPUT VIDEO CSO HSO VSO
BLACK BURST OUTPUT CVBS DIGITAL DATA GENERATOR
ADV7192
Figure 27. Possible Application for the Black Burst Output Signal
BRIGHTNESS DETECT
Figure 31. CSO, HSO, VSO Timing Diagram
COLOR BAR GENERATION
This feature is used to monitor the average brightness of the incoming Y video signal on a field by field basis. The information is read from the I2C and based on this information the color saturation, contrast and brightness controls can be adjusted (for example to compensate for very dark pictures). (Brightness Detect Register.)
CHROMA/LUMA DELAY
The ADV7192 can be configured to generate 100/7.5/75/7.5 color bars for NTSC or 100/0/75/0 color bars for PAL. (Mode Register 4.)
COLOR BURST SIGNAL CONTROL
The burst information can be switched on and off the composite and chroma video output. (Mode Register 4.)
COLOR CONTROLS
The luminance data can be delayed by maximum of six clock cycles. Additionally the Chroma can be delayed by a maximum of eight clock cycles (one clock cycle at 27 MHz). (Timing Register 0 and Mode Register 9.)
The ADV7192 allows the user to control the brightness, contrast, hue and saturation of the color. The control registers may be double-buffered, meaning that any modification to the registers will be done outside the active video region and, therefore, changes made will not be visible during active video.
Contrast Control
Contrast adjustment is achieved by scaling the Y input data by a factor programmed by the user. This factor allows the data to be scaled between 0% and 150%. (Contrast Control Register.)
CHROMA DELAY LUMA DELAY
Brightness Control
Figure 28. Chroma Delay
CLAMP OUTPUT
Figure 29. Luma Delay
The brightness is controlled by adding a programmable setup level onto the scaled Y data. This brightness level may be added onto the Y data. For NTSC with pedestal, the setup can vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and PAL, the setup can vary from -7.5 IRE to +15 IRE. (Brightness Control Register.)
Color Saturation
The ADV7192 has a programmable clamp TTL output signal. This clamp signal is programmable to the front and back porch. The clamp signal can be varied by one to three clock cycles in a positive and negative direction from the default position. (Mode Register 5, Mode Register 7.)
CLAMP O/P SIGNALS
Color adjustment is achieved by scaling the Cr and Cb input data by a factor programmed by the user. This factor allows the data to be scaled between 0% and 200%. (U Scale Register and V Scale Register.)
Hue Adjust Control
CVBS OUTPUT PIN
The hue adjustment is achieved on the composite and chroma outputs by adding a phase offset onto the color subcarrier in the active video but leaving the color burst unmodified, i.e., only the phase between the video and the colorburst is modified and hence the hue is shifted. The ADV7192 provides a range of 22 in increments of 0.17578125. (Hue Adjust Register.)
CHROMINANCE CONTROL
MR57 = 1 MR57 = 0 CLAMP OUTPUT PIN
Figure 30. Clamp Output Timing
The color information can be switched on and off the composite, chroma and color component video outputs. (Mode Register 4.) -17-
REV. 0
ADV7192
UNDERSHOOT LIMITER POWER-ON RESET
A limiter is placed after the digital filters. This prevents any synchronization problems for TVs. The level of undershoot is programmable between -1.5 IRE, -6 IRE, -11 IRE when operating in 4x Oversampling Mode. In 2x Oversampling Mode the limits are -7.5 IRE and 0 IRE. (Mode Register 9 and Timing Register 0.)
DIGITAL NOISE REDUCTION
After power-up, it is necessary to execute a RESET operation. A reset occurs on the falling edge of a high-to-low transition on the RESET pin. This initializes the pixel port such that the data on the pixel inputs pins is ignored. See Appendix 8 for the register settings after RESET is applied.
PROGRESSIVE SCAN INPUT
DNR is applied to the Y data only. A filter block selects the high frequency, low amplitude components of the incoming signal (DNR Input Select). The absolute value of the filter output is compared to a programmable threshold value (DNR Threshold Control). There are two DNR modes available: DNR Mode and DNR Sharpness Mode. In DNR Mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. A programmable amount (Coring Gain Control) of this noise signal will be subtracted from the original signal. In DNR Sharpness Mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise, as before. Otherwise, if the level exceeds the threshold, now being identified as a valid signal, a fraction of the signal (Coring Gain Control) will be added to the original signal in order to boost high frequency components and to sharpen the video image. In MPEG systems it is common to process the video information in blocks of 8 x 8 pixels for MPEG2 systems, or 16 x 16 pixels for MPEG1 systems ('Block Size Control'). DNR can be applied to the resulting block transition areas that are known to contain noise. Generally the block transition area contains two pixels. It is possible to define this area to contain four pixels (Border Area Control). It is also possible to compensate for variable block positioning or differences in YCrCb pixel timing with the use of the Block Offset Control. (Mode Register 8, DNR Registers 0-2.)
DOUBLE BUFFERING
It is possible to input data to the ADV7192 in progressive scan format. For this purpose the input pins Y0/P8-Y7/P15, Y8-Y9, Cr0-Cr9 and Cb0-Cb9 accept 10-bit Y data, 10-bit Cb data and 10-bit Cr data. The data is clocked into the part at 27 MHz. The data is then filtered and sinc corrected in an 2 Interpolation filter and then output to three video DACs at 54 MHz (to interface to a progressive scan monitor).
0 -10
-20
AMPLITUDE - dB
-30 -40
-50 -60 -70 0 5 10 15 20 FREQUENCY - MHz 25 30
Figure 32. Plot of the Interpolation Filter for the Y Data
0 -10
-20
Double buffering can be enabled or disabled on the following registers: Closed Captioning Registers, Brightness Control Register, V-Scale, U-Scale Contrast Control Register, Hue Adjust Register, Macrovision Registers, and the Gamma Curve Select bit. These registers are updated once per field on the falling edge of the VSYNC signal. Double Buffering improves the overall performance of the ADV7192, since modifications to register settings will not be made during active video, but take effect on the start of the active video. (Mode Register 8.)
GAMMA CORRECTION CONTROL
AMPLITUDE - dB
-30 -40
-50 -60 -70 0 5 10 15 20 FREQUENCY - MHz 25 30
Gamma correction may be performed on the luma data. The user has the choice to use either of two different gamma curves, A or B. At any one time one of these curves is operational if gamma correction is enabled. Gamma correction allows the mapping of the luma data to a user-defined function. (Mode Register 8, Gamma Correction Registers 0-13.)
NTSC PEDESTAL CONTROL
Figure 33. Plot of the Interpolation Filter for the CrCb Data
It is assumed that there is no color space conversion or any other such operation to be performed on the incoming data. Thus if these DAC outputs are to drive a TV, all relevant timing and synchronization data should be contained in the incoming digital Y data. The block diagram below shows a possible configuration for progressive scan mode using the ADV7192.
In NTSC mode it is possible to have the pedestal signal generated on the output video signal. (Mode Register 2.)
-18-
REV. 0
ADV7192
ENCODER ADV7192
54MHz PLL 27MHz MPEG2 PIXEL BUS ENCODER CORE I N T E R P 2O L A T I O N O U T P U T S
Resetting the SCH phase every four or eight fields avoids the accumulation of SCH phase error, and results in very minor SCH phase jumps at the start of the four or eight field sequence. Resetting the SCH phase should not be done if the video source does not have stable timing or the ADV7192 is configured in RTC mode. Under these conditions (unstable video) the Subcarrier Phase Reset should be enabled but no reset applied. In this configuration the SCH Phase will never be reset; this means that the output video will now track the unstable input video. The Subcarrier Phase Reset when applied will reset the SCH phase to Field 0 at the start of the next field (e.g., Subcarrier Phase Reset applied in Field 5 (PAL) on the start of the next field SCH phase will be reset to Field 0). (Mode Register 4.)
SLEEP MODE
6 D A C
PROGRESSIVE SCAN DECODER
30-BIT INTERFACE
Figure 34. Block Diagram Using the ADV7192 in Progressive Scan Mode
The progressive scan decoder deinterlaces the data from the MPEG2 decoder. This now means that there are 525 video lines per field in NTSC mode and 625 video lines per field in PAL mode. The duration of the video line is now 32 s. It is important to note that the data from the MPEG2 decoder is in 4:2:2 format. The data output from the progressive scan decoder is in 4:4:4 format. Thus it is assumed that some form of interpolation on the color component data is performed in the progressive scan decoder IC. (Mode Register 8.)
REAL-TIME CONTROL, SUBCARRIER RESET, AND TIMING RESET
If, after RESET, the SCRESET/RTC/TR and NTSC_PAL pins are both set high, the ADV7192 will power up in Sleep Mode to facilitate low power consumption before all registers have been initialized. If Power-up in Sleep Mode is disabled, Sleep Mode control passes to the Sleep Mode control in Mode Register 2 (i.e., control via I2C). (Mode Register 2 and Mode Register 6.)
SQUARE PIXEL MODE
Together with the SCRESET/RTC/TR pin and Mode Register 4 (Genlock Control), the ADV7192 can be used in (a) Timing Reset Mode, (b) Subcarrier Phase Reset Mode or (c) RTC Mode. (a) A TIMING RESET is achieved in holding this pin high. In this state the horizontal and vertical counters will remain reset. On releasing this pin (set to low), the internal counters will commence counting again. The minimum time the pin has to be held high is 37 ns (1 clock cycle at 27 MHz), otherwise the reset signal might not be recognized. (b) The SUBCARRIER PHASE will reset to that of Field 0 at the start of the following field when a low to high transition occurs on this input pin. (c) In RTC MODE, the ADV7192 can be used to lock to an external video source. The real-time control mode allows the ADV7192 to automatically alter the subcarrier frequency to compensate for line length variations. When the part is connected to a device that outputs a digital datastream in the RTC format (such as a ADV7185 video decoder, see Figure 38), the part will automatically change to the compensated subcarrier frequency on a line-by-line basis. This digital datastream is 67 bits wide and the subcarrier is contained in Bits 0 to 21. Each bit is two clock cycles long. 00Hex should be written into all four Subcarrier Frequency registers when using this mode. (Mode Register 4.)
SCH PHASE MODE
The ADV7192 can be used to operate in square pixel mode. For NTSC operation an input clock of 24.5454 MHz is required. Alternatively, for PAL operation, an input clock of 29.5 MHz is required. The internal timing logic adjusts accordingly for square pixel mode operation. Square pixel mode is not available in 4x Oversampling mode. (Mode Register 2.)
VERTICAL BLANKING DATA INSERTION AND BLANK INPUT
It is possible to allow encoding of incoming YCbCr data on those lines of VBI that do not have line sync or pre-/post-equalization pulses . This mode of operation is called Partial Blanking. It allows the insertion of any VBI data (Opened VBI) into the encoded output waveform, this data is present in digitized incoming YCbCr data stream (e.g., WSS data, CGMS, VPS etc.). Alternatively the entire VBI may be blanked (no VBI data inserted) on these lines. VBI is available in all timing modes. The complete VBI is comprised of the following lines: 525/60 systems, Lines 525 to 21 for field one and Lines 262 to Line 284 for field two. 625/50 systems, Lines 624 to Line 22 and Lines 311 to 335. The "Opened VBI" consists of: 525/60 systems, Lines 10 to 21 for field one and second half of Line 273 to Line 284 for field two. 625/50 systems, Lines 7 to 22 and Lines 319 to 335. (Mode Register 3.) It is possible to allow control over the BLANK signal using Timing Register 0. When the BLANK input is enabled (TR03 = 0 and input pin tied low), the BLANK input can be used to input externally generated blank signals in Slave Mode 1, 2, or 3. When the BLANK input is disabled (TR03 = 1 and input pin tied low or tied high) the BLANK input is not used and the ADV7192 automatically blanks all normally blank lines as per CCIR-624. (Timing Register 0.)
The SCH phase is configured in default mode to reset every four (NTSC) or eight (PAL) fields to avoid an accumulation of SCH phase error over time. In an ideal system, zero SCH phase error would be maintained forever, but in reality, this is impossible to achieve due to clock frequency variations. This effect is reduced by the use of a 32-bit DDS, which generates this SCH. REV. 0
-19-
ADV7192
YUV LEVELS
This functionality allows the ADV7192 to output SMPTE levels or Betacam levels on the Y output when configured in PAL or NTSC mode. Betacam SMPTE MII Sync 286 mV 300 mV 300 mV Video 714 mV 700 mV 700 mV
0dB
2 FILTER REQUIREMENTS 4 FILTER REQUIREMENTS
-30dB 6.75MHz 13.5MHz 27.0MHz 40.5MHz 54.0MHz
As the data path is branched at the output of the filters, the luma signal relating to the CVBS or S-Video Y/C output is unaltered. Only the Y output of the YCrCb outputs is scaled. This control allows color component levels to have a peak-peak amplitude of 700 mV, 1000 mV or the default values of 934 mV in NTSC and 700 mV in PAL. (Mode Register 5.)
16-BIT INTERFACE
Figure 36. Output Filter Requirements in 2x and 4x Oversampling Mode
VIDEO TIMING DESCRIPTION
It is possible to input data in 16-bit format. In this case, the interface only operates if the data is accompanied by separate HSYNC/VSYNC/BLANK signals. Sixteen-bit mode is not available in Slave Mode 0 since EAV/SAV timing codes are used. (Mode Register 8.)
4 OVERSAMPLING AND INTERNAL PLL
The ADV7192 is intended to interface to off-the-shelf MPEG1 and MPEG2 Decoders. As a consequence, the ADV7192 accepts 4:2:2 YCrCb Pixel Data via a CCIR-656 Pixel Port and has several Video Timing Modes of operation that allow it to be configured as either System Master Video Timing Generator or a Slave to the System Video Timing Generator. The ADV7192 generates all of the required horizontal and vertical timing periods and levels for the analog video outputs. The ADV7192 calculates the width and placement of analog sync pulses, blanking levels, and color burst envelopes. Color bursts are disabled on appropriate lines and serration and equalization pulses are inserted where required. In addition the ADV7192 supports a PAL or NTSC square pixel operation. The part requires an input pixel clock of 24.5454 MHz for NTSC square pixel operation and an input pixel clock of 29.5 MHz for PAL square pixel operation. The internal horizontal line counters place the various video waveform sections in the correct location for the new clock frequencies. The ADV7192 has four distinct Master and four distinct Slave timing configurations. Timing Control is established with the bidirectional HSYNC, BLANK and VSYNC pins. Timing Register 1 can also be used to vary the timing pulsewidths and where they occur in relation to each other. (Mode Register 2, Timing Register 0, 1.)
RESET SEQUENCE
It is possible to operate all six DACs at 27 MHz (2x Oversampling) or 54 MHz (4x Oversampling). The ADV7192 is supplied with a 27 MHz clock synced with the incoming data. Two options are available: to run the device throughout at 27 MHz or to enable the PLL. In the latter case, even if the incoming data runs at 27 MHz, 4x Oversampling and the internal PLL will output the data at 54 MHz. NOTE In 4x Oversampling Mode the requirements for the optional output filters are different from those in 2x Oversampling. (Mode Register 1, Mode Register 6.) See Appendix 6.
ENCODE ADV7192
2 6 D A C O U T P U T S 54MHz OUTPUT
MPEG2
PIXEL BUS 27MHz
I N T ENCODER E CORE R P O L A T I 54MHz O PLL N
When RESET becomes active the ADV7192 reverts to the default output configuration (see Appendix 8 for register settings). The ADV7192 internal timing is under the control of the logic level on the NTSC_PAL pin. When RESET is released Y, Cr, Cb values corresponding to a black screen are input to the ADV7192. Output timing signals are still suppressed at this stage. DACs A, B, C are switched off and DACs D, E, F are switched on. When the user requires valid data, Pixel Data Valid Control is enabled (MR26 = 1) to allow the valid pixel data to pass through the encoder. Digital output timing signals become active and the encoder timing is now under the control of the Timing Registers. If at this stage, the user wishes to select a different video standard to that on the NTSC_PAL pin, Standard I2C Control should be enabled (MR25 = 1) and the video standard required is selected by programming Mode Register 0 (Output Video Standard Selection). Figure 37 illustrates the RESET sequence timing.
Figure 35. PLL and 4x Oversampling Block Diagram
-20-
REV. 0
ADV7192
RESET DAC D, DAC E
XXXXXXX
XXXXXXX
BLACK VALUE WITH SYNC
VALID VIDEO
DAC F
XXXXXXX
XXXXXXX
BLACK VALUE
VALID VIDEO
DAC A, DAC B, DAC C MR26 PIXEL_DATA_VALID
XXXXXXX
OFF
VALID VIDEO
XXXXXXX
0
1
DIGITAL TIMING
XXXXXXX
DIGITAL TIMING SIGNALS SUPPRESSED
TIMING ACTIVE
Figure 37. RESET Sequence Timing Diagram
ADV7192
CLOCK COMPOSITE VIDEO e.g., VCR OR CABLE LCC1 GLL VIDEO DECODER P19-P12 M U X MPEG DECODER SCRESET/RTC/TR GREEN/COMPOSITE/Y BLUE/LUMA/U P7-P0 RED/CHROMA/V GREEN/COMPOSITE/Y BLUE/LUMA/U HSYNC VSYNC RED/CHROMA/V
ADV7185
H/L TRANSITION COUNT START 14 BITS LOW RESERVED 128 13 RTC TIME SLOT: 01
4 BITS RESERVED 0 21 FSCPLL INCREMENT1
SEQUENCE BIT2 RESET 5 BITS BIT3 RESERVED RESERVED 0
14 NOT USED IN ADV7192
19 VALID SAMPLE INVALID SAMPLE 8/LINE LOCKED CLOCK
67 68
NOTES: 1F SC PLL INCREMENT IS 22 BITS LONG, VALUE LOADED INTO ADV7192 FSC DDS REGISTER IS FSC PLL INCREMENTS BITS 21:0 PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS OF THE ADV7192. 2SEQUENCE BIT PAL: 0 = LINE NORMAL, 1 = LINE INVERTED NTSC: 0 = NO CHANGE 3RESET BIT RESET ADV7192's DDS
Figure 38. RTC Timing and Connections
REV. 0
-21-
ADV7192
Mode 0 (CCIR-656): Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0) The ADV7192 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data. All timing information is transmitted using a 4-byte Synchronization Pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 39. The HSYNC, VSYNC and BLANK (if not used) pins should be tied high during this mode. Blank output is available.
ANALOG VIDEO
EAV CODE INPUT PIXELS C F00X8181 Yr YF00Y0000 4 CLOCK 4 CLOCK 280 CLOCK END OF ACTIVE VIDEO LINE 0 F FAAA 0 F FBBB ANCILLARY DATA (HANC) 268 CLOCK
SAV CODE 8181F00XC C C C C 0000F00YbYr YbYr Yb 4 CLOCK 1440 CLOCK 4 CLOCK 1440 CLOCK START OF ACTIVE VIDEO LINE
NTSC/PAL M SYSTEM (525 LlNES/60Hz) PAL SYSTEM (625 LINES/50Hz)
Figure 39. Timing Mode 0, Slave Mode
Mode 0 (CCIR-656): Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1) The ADV7192 generates H, V, and F signals required for the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is output on the VSYNC pin. Mode 0 is illustrated in Figure 40 (NTSC) and Figure 41 (PAL). The H, V, and F transitions relative to the video waveform are illustrated in Figure 42.
DISPLAY DISPLAY VERTICAL BLANK
522 H V F
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
EVEN FIELD
ODD FIELD
DISPLAY VERTICAL BLANK
DISPLAY
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
H V F
ODD FIELD EVEN FIELD
Figure 40. Timing Mode 0, NTSC Master Mode
-22-
REV. 0
ADV7192
DISPLAY DISPLAY VERTICAL BLANK
622 H V F
623
624
625
1
2
3
4
5
6
7
21
22
23
EVEN FIELD
ODD FIELD
DISPLAY VERTICAL BLANK
DISPLAY
309 H V F
310
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
EVEN FIELD
Figure 41. Timing Mode 0, PAL Master Mode
ANALOG VIDEO
H F V
Figure 42. Timing Mode 0 Data Transitions, Master Mode
REV. 0
-23-
ADV7192
Mode 1: Slave Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 0) In this mode the ADV7192 accepts Horizontal SYNC and Odd/ Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7192 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 43 (NTSC) and Figure 44 (PAL).
DISPLAY DISPLAY VERTICAL BLANK
522 HSYNC BLANK FIELD
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY VERTICAL BLANK
260 HSYNC BLANK FIELD
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
Figure 43. Timing Mode 1, NTSC
DISPLAY
VERTICAL BLANK
DISPLAY
622 HSYNC BLANK FIELD
623
624
625
1
2
3
4
5
6
7
21
22
23
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY VERTICAL BLANK
309 HSYNC BLANK FIELD
310
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
EVEN FIELD
Figure 44. Timing Mode 1, PAL
-24-
REV. 0
ADV7192
Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1) In this mode the ADV7192 can generate Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7192 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 43 (NTSC) and Figure 44 (PAL). Figure 45 illustrates the HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data.
HSYNC FIELD PAL = 12 CLOCK/2 NTSC = 16 CLOCK/2 BLANK PIXEL DATA PAL = 132 CLOCK/2 NTSC = 122 CLOCK/2 Cb Y Cr Y
Figure 45. Timing Mode 1 Odd/Even Field Transitions Master/Slave
Mode 2: Slave Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 0) In this mode the ADV7192 accepts Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. The BLANK signal is optional. When the BLANK input is disabled the ADV7192 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 46 (NTSC) and Figure 47 (PAL).
DISPLAY VERTICAL BLANK DISPLAY
522 HSYNC BLANK VSYNC
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY VERTICAL BLANK
260 HSYNC BLANK VSYNC
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
Figure 46. Timing Mode 2, NTSC
REV. 0
-25-
ADV7192
DISPLAY VERTICAL BLANK DISPLAY
622 HSYNC BLANK VSYNC
623
624
625
1
2
3
4
5
6
7
21
22
23
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY VERTICAL BLANK
309 HSYNC BLANK VSYNC
310
311
312
313
314
315
316
317
318
319
320
334
335
336
ODD FIELD
EVEN FIELD
Figure 47. Timing Mode 2, PAL
Mode 2: Master Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 1) In this mode the ADV7192 can generate Horizontal and Vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of an Even Field. The BLANK signal is optional. When the BLANK input is disabled the ADV7192 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 46 (NTSC) and Figure 47 (PAL). Figure 48 illustrates the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 49 illustrates the HSYNC, BLANK and VSYNC for an odd-to-even field transition relative to the pixel data.
HSYNC
VSYNC
PAL = 12 CLOCK/2 NTSC = 16 CLOCK/2
BLANK
PIXEL DATA PAL = 132 CLOCK/2 NTSC = 122 CLOCK/2
Cb
Y
Cr
Y
Figure 48. Timing Mode 2, Even-to-Odd Field Transition Master/Slave
HSYNC
VSYNC
PAL = 12 CLOCK/2 NTSC = 16 CLOCK/2
PAL = 864 CLOCK/2 NTSC = 858 CLOCK/2
BLANK
PIXEL DATA PAL = 132 CLOCK/2 NTSC = 122 CLOCK/2
Cb
Y
Cr
Y
Cb
Figure 49. Timing Mode 2, Odd-to-Even Field Transition Master/Slave
-26-
REV. 0
ADV7192
Mode 3: Master/Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode the ADV7192 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7192 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 50 (NTSC) and Figure 51 (PAL).
DISPLAY VERTICAL BLANK DISPLAY
522 HSYNC BLANK FIELD
523
524
525
1
2
3
4
5
6
7
8
9
10
11
20
21
22
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY VERTICAL BLANK
260 HSYNC BLANK FIELD
261
262
263
264
265
266
267
268
269
270
271
272
273
274
283
284
285
ODD FIELD
EVEN FIELD
Figure 50. Timing Mode 3, NTSC
DISPLAY
VERTICAL BLANK
DISPLAY
622 HSYNC BLANK FIELD
623
624
625
1
2
3
4
5
6
7
21
22
23
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY VERTICAL BLANK
309 HSYNC BLANK FIELD
310
311
312
313
314
315
316
317
318
319
320
334
335
336
EVEN FIELD
ODD FIELD
Figure 51. Timing Mode 3, PAL
REV. 0
-27-
ADV7192
MPU PORT DESCRIPTION
The ADV7192 support a two-wire serial (I2 C-compatible) microprocessor bus driving multiple peripherals. Two inputs, Serial Data (SDA) and Serial Clock (SCL), carry information between any device connected to the bus. Each slave device is recognized by a unique address. The ADV7192 has four possible slave addresses for both read and write operations. These are unique addresses for each device and are illustrated in Figure 52 and Figure 54. The LSB sets either a read or write operation. Logic Level 1 corresponds to a read operation while Logic Level 0 corresponds to a write operation. A1 is set by setting the ALSB pin of the ADV7192 to Logic Level 0 or Logic Level 1. When ALSB is set to 0, there is greater input bandwidth on the I2C lines, which allows high speed data transfers on this bus. When ALSB is set to 1, there is reduced input bandwidth on the I2C lines, which means that pulses of less than 50 ns will not pass into the I2C internal controller. This mode is recommended for noisy systems.
1 1 0 1 0 1 A1 ADDRESS CONTROL SETUP BY ALSB READ/WRITE CONTROL 0 WRITE 1 READ X
The ADV7192 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long supporting the 7-bit addresses plus the R/W bit. It interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses autoincrement allowing data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without having to update all the registers. There is one exception. The Subcarrier Frequency Registers should be updated in sequence, starting with Subcarrier Frequency Register 0. The autoincrement function should be then used to increment and access Subcarrier Frequency Registers 1, 2, and 3. The Subcarrier Frequency Registers should not be accessed independently. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, then, these cause an immediate jump to the idle condition. During a given SCL high period the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV7192 will not issue an acknowledge and will return to the idle condition. If, in autoincrement mode, the user exceeds the highest subaddress, then the following action will be taken: 1. In Read Mode, the highest subaddress register contents will continue to be output until the master device issues a no-acknowledge. This indicates the end of a read. A no-acknowledge condition is where the SDA line is not pulled low on the ninth pulse. 2. In Write Mode, the data for the invalid byte will be not be loaded into any subaddress register, a no-acknowledge will be issued by the ADV7192 and the part will return to the idle condition.
SDATA SCLOCK
Figure 52. Slave Address
To control the various devices on the bus the following protocol must be followed. First, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that an address/ data stream will follow. All peripherals respond to the start condition and shift the next eight bits (7-bit address + R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCL lines waiting for the start condition and the correct transmitted address. The R/W bit determines the direction of the data. A Logic 0 on the LSB of the first byte means that the master will write information to the peripheral. A Logic 1 on the LSB of the first byte means that the master will read information from the peripheral.
S
17
8
9
17
8
9
17 DATA
8
9 ACK
P STOP
START ADDR R/W ACK SUBADDRESS ACK
Figure 53. Bus Data Transfer
Figure 53 illustrates an example of data transfer for a read sequence and the start and stop conditions. Figure 54 shows bus write and read sequences.
WRITE SEQUENCE
S
SLAVE ADDR A(S) LSB = 0
SUB ADDR
A(S)
DATA
A(S) LSB = 1
DATA
A(S) P
READ SEQUENCE
S
SLAVE ADDR A(S) S = START BIT P = STOP BIT
SUB ADDR
A(S) S SLAVE ADDR
A(S)
DATA
A(M)
DATA
A(M) P
A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO ACKNOWLEDGE BY SLAVE A(M) = NO ACKNOWLEDGE BY MASTER
Figure 54. Write and Read Sequences
-28-
REV. 0
ADV7192
REGISTER ACCESSES Subaddress Register (SR7-SR0)
The MPU can write to or read from all of the registers of the ADV7192 with the exception of the Subaddress Registers which are write only registers. The Subaddress Register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the Subaddress Register. Then a read/write operation is performed from/to the target address which then increments to the next address until a stop command on the bus is performed.
REGISTER PROGRAMMING
The Communications Register is an eight bit write-only register. After the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The Subaddress Register determines to/from which register the operation takes place. Figure 55 shows the various operations under the control of the Subaddress Register 0 should always be written to SR7.
Register Select (SR6-SR0)
These bits are set up to point to the required starting address.
The following section describes each register. All registers can be read from as well as written to.
SR7 SR7 ZERO SHOULD BE WRITTEN HERE SR6 SR5 SR4 SR3 SR2 SR1 SR0
ADV7192 SUBADDRESS REGISTER ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH SR6 SR5 SR4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 SR3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 SR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 SR1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 SR0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MODE REGISTER 0 MODE REGISTER 1 MODE REGISTER 2 MODE REGISTER 3 MODE REGISTER 4 MODE REGISTER 5 MODE REGISTER 6 MODE REGISTER 7 MODE REGISTER 8 MODE REGISTER 9 TIMING REGISTER 0 TIMING REGISTER 1 SUBCARRIER FREQUENCY REGISTER 0 SUBCARRIER FREQUENCY REGISTER 1 SUBCARRIER FREQUENCY REGISTER 2 SUBCARRIER FREQUENCY REGISTER 3 SUBCARRIER PHASE REGISTER CLOSED CAPTIONING EXTENDED DATA BYTE 0 CLOSED CAPTIONING EXTENDED DATA BYTE 1 CLOSED CAPTIONING DATA BYTE 0 CLOSED CAPTIONING DATA BYTE 1 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 0 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 1 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 2 NTSC PEDESTAL/TELETEXT CONTROL REGISTER 3 CGMS/WSS 0 CGMS/WSS 1 CGMS/WSS 2 TELETEXT REQUEST CONTROL REGISTER CONTRAST CONTROL REGISTER U SCALE REGISTER V SCALE REGISTER HUE ADJUST CONTROL REGISTER BRIGHTNESS CONTROL REGISTER SHARPNESS RESPONSE REGISTER DNR REGISTER 0 DNR REGISTER 1 DNR REGISTER 2 GAMMA CORRECTION REGISTER 0 GAMMA CORRECTION REGISTER 1 GAMMA CORRECTION REGISTER 2 GAMMA CORRECTION REGISTER 3 GAMMA CORRECTION REGISTER 4 GAMMA CORRECTION REGISTER 5 GAMMA CORRECTION REGISTER 6 GAMMA CORRECTION REGISTER 7 GAMMA CORRECTION REGISTER 8 GAMMA CORRECTION REGISTER 9 GAMMA CORRECTION REGISTER 10 GAMMA CORRECTION REGISTER 11 GAMMA CORRECTION REGISTER 12 GAMMA CORRECTION REGISTER 13 BRIGHTNESS DETECT REGISTER OUTPUT CLOCK REGISTER RESERVED RESERVED RESERVED RESERVED MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER MACROVISION REGISTER
Figure 55. Subaddress Register for the ADV7192
REV. 0
-29-
ADV7192
MODE REGISTER 0 MR0 (MR07-MR00) (Address (SR4-SR0) = 00H) MODE REGISTER 1 MR1 (MR17-MR10) (Address (SR4-SR0) = 01H)
Figure 56 shows the various operations under the control of Mode Register 0.
MR0 BIT DESCRIPTION Output Video Standard Selection Control (MR00-MR01)
Figure 57 shows the various operations under the control of Mode Register 1.
MR1 BIT DESCRIPTION DAC Control (MR10-MR15)
These bits are used to set up the encoder mode. The ADV7192 can be set up to output NTSC, PAL (B, D, G, H, I), PAL M or PAL N standard video.
Luminance Filter Select (MR02-MR04)
Bits MR15-MR10 can be used to power-down the DACs. This are used to reduce the power consumption of the ADV7192 or if any of the DACs are not required in the application.
4 Oversampling Control (MR16)
These bits specify which luma filter is to be selected. The filter selection is made independent of whether PAL or NTSC is selected.
Chrominance Filter Select (MR05-MR07)
To enable 4x Oversampling this bit has to be set to 1. When enabled, the data is output at a frequency of 54 MHz. Note that PLL Enable Control has to be enabled (MR61 = 0) in 4x Oversampling mode. An external VREF is not recommended in that mode.
Reserved (MR17)
These bits select the chrominance filter. A low-pass filter can be selected with a choice of cutoff frequencies (0.65 MHz, 1.0 MHz, 1.3 MHz, 2 MHz, or 3 MHz) along with a choice of CIF or QCIF filters.
MR07 MR06 MR05 MR04
A Logical 0 must be written to this bit.
MR03
MR02
MR01
MR00
CHROMA FILTER SELECT MR07 MR06 MR05 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1.3 MHz LOW-PASS FILTER 0.65 MHz LOW-PASS FILTER 1.0 MHz LOW-PASS FILTER 2.0 MHz LOW-PASS FILTER RESERVED CIF QCIF 3.0 MHz LOW-PASS FILTER LUMA FILTER SELECT MR04 MR03 MR02 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
OUTPUT VIDEO STANDARD SELECTION MR01 MR00 0 0 1 1 0 1 0 1 NTSC PAL (B, D, G, H, I) PAL (M) PAL (N)
LOW-PASS FILTER (NTSC) LOW-PASS FILTER (PAL) NOTCH FILTER (NTSC) NOTCH FILTER (PAL) EXTENDED MODE CIF QCIF RESERVED
Figure 56. Mode Register 0, MR0
MR17 MR17 ZERO MUST BE WRITTEN TO THIS BIT
MR16
MR15 DAC A DAC CONTROL
MR14
MR13 DAC C DAC CONTROL
MR12
MR11 DAC E DAC CONTROL MR11 0 1
MR10
MR15 0 1 POWER-DOWN NORMAL
MR13 0 1 POWER-DOWN NORMAL
POWER-DOWN NORMAL DAC F DAC CONTROL MR10 0 1 POWER-DOWN NORMAL
4 MR16 0 1
OVERSAMPLING CONTROL 2 4 OVERSAMPLING OVERSAMPLING 0 1
DAC B DAC CONTROL MR14 POWER-DOWN NORMAL 0 1
DAC D DAC CONTROL MR12 POWER-DOWN NORMAL
Figure 57. Mode Register 1, MR1
-30-
REV. 0
ADV7192
MODE REGISTER 2 MR2 (MR27-MR20) (Address (SR4-SR0) = 02H) Standard I2C Control (MR25)
Mode Register 2 is an 8-bit-wide register. Figure 58 shows the various operations under the control of Mode Register 2.
MR2 BIT DESCRIPTION--RGB/YUV Control (MR20)
This bit controls the video standard used by the ADV7192. When this bit is set to 1 the video standard is as programmed in Mode Register 0 (Output Video Standard Selection). When it is set to 0, the ADV7192 is forced into the standard selected by the NTSC_PAL pin. When NTSC_PAL is low, the standard is NTSC, when the NTSC_PAL pin is high, the standard is PAL.
Pixel Data Valid Control (MR26)
This bit enables the output from the DACs to be set to YUV or RGB output video standard.
DAC Output Control (MR21)
This bit controls the output from DACs A, B, and C. When this bit is set to 1, Composite, Luma and Chroma Signals are output from DACs A, B, and C (respectively). When this bit is set to 0, RGB or YUV may be output from these DACs.
SCART Enable Control (MR22)
After resetting the device this bit has the value 0 and the pixel data input to the encoder is blanked such that a black screen is output from the DACs. The ADV7192 will be set to Master Mode timing. When this bit is set to 1 by the user (via the I2C), pixel data passes to the pins and the encoder reverts to the timing mode defined by Timing Register 0.
Sleep Mode Control (MR27)
This bit is used to switch the DAC outputs from SCART to a EUROSCART configuration. A complete table of all DAC output configurations is shown below.
Pedestal Control (MR23)
When this bit is set (1), Sleep Mode is enabled. With this mode enabled, the ADV7192 current consumption is reduced to typically 0.1 A. The I2C registers can be written to and read from when the ADV7192 is in Sleep Mode. When the device is in Sleep Mode and 0 is written to MR27, the ADV7192 will come out of Sleep Mode and resume normal operation. Also, if a RESET is applied during Sleep Mode the ADV7192 will come out of Sleep Mode and resume normal operation. For this to operate Power up in Sleep Mode control has to be enabled (MR60 is set to a Logic 0), otherwise Sleep Mode is controlled by the PAL_NTSC and SCRESET/RTC/TR pins.
This bit specifies whether a pedestal is to be generated on the NTSC composite video signal. This bit is invalid when the device is configured in PAL mode.
Square Pixel Control (MR24)
This bit is used to set up square pixel mode. This is available in Slave Mode only. For NTSC, a 24.54 MHz clock must be supplied. For PAL, a 29.5 MHz clock must be supplied. Square pixel operation is not available in 4x Oversampling mode.
MR27
MR26 PIXEL DATA VALID CONTROL MR26 0 DISABLE 1 ENABLE
MR25
MR24 SQUARE PIXEL CONTROL MR24 0 DISABLE 1 ENABLE
MR23
MR22 SCART ENABLE CONTROL MR22 0 DISABLE 1 ENABLE
MR21
MR20 RGB/YUV CONTROL
MR20 0 RGB OUTPUT 1 YUV OUTPUT DAC OUTPUT CONTROL
SLEEP MODE CONTROL MR27 0 DISABLE 1 ENABLE
STANDARD I2C CONTROL MR25 0 DISABLE 1 ENABLE
PEDESTAL CONTROL MR23 0 PEDESTAL OFF 1 PEDESTAL ON
MR21 0 RGB/YUV/COMP 1 COMP/LUMA/CHROMA
Figure 58. Mode Register 2, MR2
Table III. DAC Output Configuration
MR22 0 0 0 0 1 1 1 1
MR21 0 0 1 1 0 0 1 1
MR20 0 1 0 1 0 1 0 1
DAC A G (Y) Y (Y) CVBS CVBS CVBS CVBS CVBS CVBS
DAC B B (Pb) U (Pb) LUMA LUMA B (Pb) U (Pb) LUMA LUMA
DAC C R (Pr) V (Pr) CHROMA CHROMA R (Pr) V (Pr) CHROMA CHROMA
DAC D CVBS CVBS G (Y) Y (Y) G (Y) Y (Y) G (Y) Y (Y)
DAC E LUMA LUMA B (Pb) U (Pb) LUMA LUMA B (Pb) U (Pb)
DAC F CHROMA CHROMA R (Pr) V (Pr) CHROMA CHROMA R (Pr) V (Pr)
NOTE In Progressive Scan Mode (MR80 = 1) the DAC output configuration is stated in the brackets.
REV. 0
-31-
ADV7192
MODE REGISTER 3 MR3 (MR37-MR30) (Address (SR4-SR0) = 03H) Genlock Control (MR41-MR42)
Mode Register 3 is an 8-bit-wide register. Figure 59 shows the various operations under the control of Mode Register 3.
MR3 BIT DESCRIPTION Revision Code (MR30-MR31)
These bits control the Genlock feature and timing reset of the ADV7192. Setting MR41 and MR42 to Logic 0 disables the SCRESET/RTC/TR pin and allows the ADV7192 to operate in normal mode. 1. By setting MR41 to zero and MR42 to one, a timing reset is applied, resetting the horizontal and vertical counters. This has the effect of resetting the Field Count to Field 0. If the SCRESET/RTC/TR pin is held high, the counters will remain reset. Once the pin is released the counters will commence counting again. For correct counter reset, the SCRESET/RTC/TR pin has to remain high for at least 37 ns (one clock cycle at 27 MHz). 2. If MR41 is set to one and MR42 is set to zero, the SCRESET/ RTC/TR pin is configured as a subcarrier reset input and the subcarrier phase will reset to Field 0 whenever a low-tohigh transition is detected on the SCRESET/RTC/TR pin (SCH phase resets at the start of the next field). 3. If MR41 is set to one and MR42 is set to one, the SCRESET/ RTC/TR pin is configured as a real time control input and the ADV7192 can be used to lock to an external video source working in RTC mode. See Real-Time Control, Subcarrier Reset and Timing Reset section.
Active Video Line Duration (MR43)
This bit is read only and indicates the revision of the device.
VBI Open (MR32)
This bit determines whether or not data in the Vertical Blanking Interval (VBI) is output to the analog outputs or blanked. Note that this condition is also valid in Timing Slave Mode 0. For further information see Vertical Blanking Data Insertion and BLANK Input section.
Teletext Enable (MR33)
This bit must be set to 1 to enable teletext data insertion on the TTX pin. Note: TTX functionality is shared with VSO and CLAMP on Pin 62. CLAMP/VSO Select (MR77) and TTX Input/CLAMP-VSO Output (MR76) have to be set accordingly.
Teletext Bit Request Mode Control (MR34)
This bit enables switching of the teletext request signal from a continuous high signal (MR34 = 0) to a bitwise request signal (MR34 = 1).
Closed Captioning Field Selection (MR35-MR36)
These bits control the fields that closed captioning data is displayed on, closed captioning information can be displayed on an odd field, even field or both fields.
Reserved (MR37)
This bit switches between two active video line durations. A zero selects CCIR Rec. 601 (720 pixels PAL/NTSC) and a one selects ITU-R BT. 470 standard for active video duration (710 pixels NTSC, 702 pixels PAL).
Chrominance Control (MR44)
A Logic 0 must be written to this bit.
MODE REGISTER 4 MR4 (MR47-MR40) (Address (SR4-SR0) = 04H)
This bit enables the color information to be switched on and off the chroma, composite and color component outputs.
Burst Control (MR45)
Mode Register 4 is an 8-bit-wide register. Figure 60 shows the various operations under the control of Mode Register 4.
MR4 BIT DESCRIPTION VSYNC_3H Control (MR40)
This bit enables the color burst to be switched on and off the chroma and composite outputs.
Color Bar Control (MR46)
When this bit is enabled (1) in Slave Mode, it is possible to drive the VSYNC input low for 2.5 lines in PAL mode and three lines in NTSC mode. When this bit is enabled in Master Mode the ADV7192 outputs an active low VSYNC signal for three lines in NTSC mode and 2.5 lines in PAL mode.
This bit can be used to generate and output an internal color bar test pattern. The color bar configuration is 100/7.5/75/7.5 for NTSC and 100/0/75/0 for PAL. It is important to note that when color bars are enabled the ADV7192 is configured in a Master Timing mode. The output pins VSYNC, HSYNC and BLANK are three-state during color bar mode.
Interlaced Mode Control (MR47)
This bit is used to setup the output to interlaced or noninterlaced mode.
MR33 MR32 MR31 MR30
MR37
MR36
MR35
MR34 TTX BIT REQUEST MODE CONTROL MR34 0 DISABLE 1 ENABLE
MR37 ZERO MUST BE WRITTEN TO THIS BIT
VBI OPEN MR32 0 DISABLE 1 ENABLE
MR31 MR30 RESERVED FOR REVISION CODE
CLOSED CAPTIONING FIELD SELECTION MR36 MR35 0 0 0 1 1 0 1 1 NO DATA OUT ODD FIELD ONLY EVEN FIELD ONLY DATA OUT (BOTH FIELDS)
TELETEXT ENABLE MR33 0 DISABLE 1 ENABLE
Figure 59. Mode Register 3, MR3
-32-
REV. 0
ADV7192
MR47 MR46 MR45 MR44 MR43 MR42 MR41 MR40 COLOR BAR CONTROL MR46 0 DISABLE 1 ENABLE CHROMINANCE CONTROL MR44 0 ENABLE COLOR 1 DISABLE COLOR GENLOCK CONTROL MR42 MR41 0 0 1 1 INTERLACE MODE CONTROL MR47 0 INTERLACED 1 NONINTERLACED BURST CONTROL MR45 0 ENABLE BURST 1 DISABLE BURST ACTIVE VIDEO LINE DURATION MR43 0 720 PIXELS 1 710 PIXELS/702 PIXELS 0 1 0 1 DISABLE GENLOCK ENABLE SUBCARRIER RESET PIN TIMING RESET ENABLE RTC PIN VSYNC 3H CONTROL MR40 0 DISABLE 1 ENABLE
Figure 60. Mode Register 4, MR4
MODE REGISTER 5 MR5 (MR57-MR50) (Address (SR4-SR0) = 05H)
RGB Sync (MR53)
This bit is used to set up the RGB outputs with the sync information encoded on all RGB outputs.
Clamp Delay (MR54-MR55)
Mode Register 5 is a 8-bit-wide register. Figure 61 shows the various operations under the control of Mode Register 5.
MR5 BIT DESCRIPTION Y-Level Control (MR50)
These bits control the delay or advance of the CLAMP signal in the front or back porch of the ADV7192. It is possible to delay or advance the pulse by zero, one, two or three clock cycles. Note: TTX functionality is shared with VSO and CLAMP on Pin 62. CLAMP/VSO Select (MR77) and TTX Input/CLAMP-VSO Output (MR76) have to be set accordingly.
Clamp Delay Direction (MR56)
This bit controls the component Y output level on the ADV7192 If this bit is set (0), the encoder outputs Betacam levels when configured in PAL or NTSC mode. If this bit is set (1), the encoder outputs SMPTE levels when configured in PAL or NTSC mode.
UV-Levels Control (MR51-MR52)
These bits control the component U and V output levels on the ADV7192. It is possible to have UV levels with a peak-to-peak amplitude of either 700 mV (MR52 + MR51 = 01) or 1000 mV (MR52 + MR51 = 10) in NTSC and PAL. It is also possible to have default values of 934 mV for NTSC and 700 mV for PAL (MR52 + MR51 = 00).
This bit controls a positive or negative delay in the CLAMP signal. If this bit is set (1), the delay is negative. If it is set (0), the delay is positive.
Clamp Position (MR57)
This bit controls the position of the CLAMP signal. If this bit is set (1), the CLAMP signal is located in the back porch position. If this bit is set (0), the CLAMP signal is located in the front porch position.
MR57
MR56 CLAMP DELAY DIRECTION MR56 0 POSITIVE 1 NEGATIVE
MR55
MR54
MR53
MR52
MR51
MR50 Y LEVEL CONTROL
RGB SYNC MR53 0 1 CLAMP DELAY DISABLE ENABLE
MR50 0 DISABLE 1 ENABLE UV LEVEL CONTROL
CLAMP POSITION MR57 0 FRONT PORCH 1 BACK PORCH
MR55 MR54 0 0 1 1 0 1 0 1 NO DELAY 1 PCLK 2 PCLK 3 PCLK
MR52 MR51 0 0 1 1 0 1 0 1 DEFAULT LEVELS 700mV 1000mV RESERVED
Figure 61. Mode Register 5, MR5
REV. 0
-33-
ADV7192
MR67 MR66 MR65 MR64 MR63 MR62 MR61 MR60
MR67 MR66 MR65 FIELD COUNTER
MR64 MR63 MR62 ZERO MUST BE WRITTEN TO THESE BITS
PLL ENABLE CONTROL MR61 0 1 ENABLED DISABLED
POWER-UP SLEEP MODE CONTROL MR60 0 ENABLED 1 DISABLED
Figure 62. Mode Register 6, MR6
Mode Register 6 MR6 (MR67-MR60) (Address (SR4-SR0) = 06H) Luma Saturation Control (MR71)
Mode Register 6 is a 8-bit-wide register. Figure 62 shows the various operations under the control of Mode Register 6.
MR6 BIT DESCRIPTION Power-Up Sleep Mode Control (MR60)
When this bit is set (1), the luma signal will be clipped if it reaches a limit that corresponds to an input luma value of 255 (after scaling by the Contrast Control Register). This prevents the chrominance component of the composite video signal being clipped if the amplitude of the luma is too high. When this bit is set (0), this control is disabled.
Hue Adjust Control (MR72)
After RESET is applied this control is enabled (MR60 = 0) if both SCRESET/RTC/TR and NTSC_PAL pins are tied high. The ADV7192 will then power up in Sleep Mode to facilitate low power consumption before the I2C is initialized. When this control is disabled (MR60 = 1, via the I2C) Sleep Mode control passes to Sleep Mode Control, MR27.
PPL Enable Control (MR61)
This bit is used to enable hue adjustment on the composite and chroma output signals of the ADV7192. When this bit is set (1), the hue of the color is adjusted by the phase offset described in the Hue Adjust Control Register. When this bit is set (0), hue adjustment is disabled.
Brightness Enable Control (MR73)
The PLL control should be enabled (MR61 = 0 ) when 4x Oversampling is enabled (MR16 = 1). When this bit is toggled, it is also used to reset the PLL.
Reserved (MR62, MR63, MR64)
This bit is used to enable brightness control on the ADV7192. The actual brightness level is programmed in the Brightness Control Register. This value or set-up level is added to the scaled Y data. When this bit is set (1), brightness control is enabled. When this bit is set (0), brightness control is disabled.
Sharpness Filter Enable (MR74)
A Logical 0 must be written to these bits.
Field Counter (MR65, MR66, MR67)
These three bits are read only bits. The field count can be read back over the I2C interface. In NTSC mode the field count goes from 0-3, in PAL Mode from 0-7.
MODE REGISTER 7 MR7 (MR77-MR70) (Address (SR4-SR0) = 07H)
This bit is used to enable the sharpness control of the luminance signal on the ADV7192 (Luma Filter Select has to be set to Extended, MR04-MR02 = 100). The various responses of the filter are determined by the Sharpness Control Register. When this bit is set (1), the luma response is altered by the amount described in the Sharpness Control Register. When this bit is set (0), the sharpness control is disabled. See Internal Filter Response section for luma signal responses.
CSO_HSO Output Control (MR75)
Mode Register 7 is a 8-bit-wide register. Figure 63 shows the various operations under the control of Mode Register 7.
MR7 BIT DESCRIPTION Color Control Enable (MR70)
This bit is used to enable control of contrast and saturation of color. If this bit is set (1) color controls are enabled (Contrast Control Register, U-Scale Register, V-Scale Register). If this bit is set (0), the color control features are disabled.
This bit is used to determine whether HSO or CSO TTL output signal is output at the CSO_HSO pin. If this bit is set (1), the CSO TTL signal is output. If this bit is set (0), the HSO TTL signal is output.
TTX Input/CLAMP-VSO Output (MR76)
This bit controls whether Pin 62 is configured as an output or as an input pin. A 1 selects Pin 62 to be an output for CLAMP or VSO functionality. A 0 selects this pin as a TTX input pin.
MR73 MR72 HUE ADJUST CONTROL MR72 0 1 DISABLE ENABLE MR71 MR70
MR77
MR76
MR75
MR74
TTX INPUT/CLAMP-VSO OUTPUT CONTROL MR76 0 1 CLAMP/ VSO SELECT MR77 0 1 VSO OUTPUT CLAMP OUTPUT TTX INPUT CLAMP/VSO OUTPUT
SHARPNESS FILTER ENABLE MR74 0 1 DISABLE ENABLE
COLOR CONTROL ENABLE MR70 0 DISABLE 1 ENABLE
CSO_HSO OUTPUT CONTROL MR75 0 1 HSO OUT CSO OUT
BRIGHTNESS ENABLE CONTROL MR73 0 1 DISABLE ENABLE
LUMA SATURATION CONTROL MR71 0 1 DISABLE ENABLE
Figure 63. Mode Register 7, MR7
-34-
REV. 0
ADV7192
MR87 MR86 GAMMA ENABLE CONTROL MR86 0 DISABLE 1 ENABLE GAMMA CURVE SELECT CONTROL MR87 0 CURVE A 1 CURVE B MR85 MR84 MR84 ZERO SHOULD BE WRITTEN TO THIS BIT MR83 MR82 DOUBLE BUFFER CONTROL MR82 0 DISABLE 1 ENABLE MR81 ZERO SHOULD BE WRITTEN TO THIS BIT MR81 MR80 PROGRESSIVE SCAN CONTROL MR80 0 DISABLE 1 ENABLE
DNR ENABLE CONTROL MR85 0 DISABLE 1 ENABLE
16-PIXEL PORT CONTROL MR83 0 DISABLE 1 ENABLE
Figure 64. Mode Register 8, MR8
CLAMP/VSO Select (MR77)
This bit is used to select the functionality of Pin 62. Setting this bit to 1 selects CLAMP as the output signal. A 0 selects VSO as the output signal. Since this pin is also shared with the TTX functionality, TTX Input/CLAMP-VSO Output has to be set accordingly (MR76).
MODE REGISTER 8 MR8 (MR87-MR80) (Address (SR4-SR0) = 08H)
selected is Curve A. Otherwise, Curve B is selected. Each curve will have to be programmed by the user. For further information on Gamma Correction controls see Gamma Correction Registers section.
MODE REGISTER 9 MR9 (MR97-MR90) (Address (SR4-SR0) = 09H)
Mode Register 9 is an 8-bit-wide register. Figure 66 shows the various operations under the control of Mode Register 9.
MR9 BIT DESCRIPTION Undershoot Limiter (MR90-MR91)
Mode Register 8 is an 8-bit-wide register. Figure 64 shows the various operations under the control of Mode Register 8.
MR8 BIT DESCRIPTION Progressive Scan Control (MR80)
This control enables the progressive scan inputs on pins Y(0)/P8-Y(7)/P15, Y(8)-Y(9), Cr(0)-Cr(9), Cb(0)-Cb(9). To enable this control MR80 has to be set to 1. It is assumed that the incoming Y data contains all necessary sync information. Note: Simultaneous progressive scan input and 16-bit pixel input is not possible.
Reserved (MR81)
This control ensures that no luma video data will go below a programmable level. This prevents any synchronization problems due to luma signals going below the blanking level. Available limit levels are -1.5 IRE, -6 IRE, -11 IRE. Note that this facility is only available in 4x Oversampling mode (MR16 = 1). When the device is operated in 2x Oversampling mode (MR16 = 0) or RGB output without RGB sync are selected, the minimum luma level is set in Timing Register 0, TR06 (Min Luma Control).
Black Burst Y DAC (MR92)
A 0 must be written to this bit.
Double Buffer Control (MR82)
Double Buffering can be enabled or disabled on the Contrast Control Register, U Scale Register, V Scale Register, Hue Adjust Control Register, Closed Captioning Register, Brightness Control Register, Gamma Curve Select Bit and the Macrovision Registers. Double Buffer is not available in Master Mode.
16-Bit Pixel Port (MR83)
It is possible to output a Black Burst signal from the DAC which is selected to be the Luma DAC (MR22, MR21, MR20). This signal can be useful for locking two video sources together using professional video equipment. See also Black Burst Output section.
Black Burst Luma (MR93)
This bit controls if the ADV7192 is operated in 8-bit or 16-bit mode. In 8-bit mode the input data will be set up on Pins P0-P7.
Reserved (MR84)
It is possible to output a Black Burst signal from the DAC which is selected to be the Y-DAC (MR22, MR21, MR20). This signal can be useful for locking two video sources together using professional video equipment. See also Black Burst Output section.
3.58MHz COLOR BURST (9 CYCLES) 20 IRE 0 IRE -20 IRE -40 IRE 4.43MHz COLOR BURST (10 CYCLES) 21.5 IRE 0 IRE -21.5 IRE -43 IRE
A Logic 0 must be written to this bit.
DNR Enable Control (MR85)
NTSC BLACK BURST SIGNAL
To enable the DNR process this bit has to be set to 1. If this bit is set to other DNR processing is bypassed. For further information on DNR controls see DNR Mode Control section.
Gamma Enable Control (MR86)
PAL BLACK BURST SIGNAL
To enable the programmable gamma correction this bit has to be set to enabled (MR86 = 1). For further information on Gamma Correction controls see Gamma Correction Registers section.
Gamma Curve Select Control (MR87)
Figure 65. Black Burst Signals for PAL and NTSC Standards
This bit selects which of the two programmable gamma curves is to be used. When setting MR87 to 0, the gamma correction curve REV. 0 -35-
ADV7192
MR97 MR96 MR95 MR94 MR93 MR92 MR91 MR90
MR97 MR96 ZERO MUST BE WRITTEN TO THESE BITS
CHROMA DELAY CONTROL MR95 MR94 0 0 1 1 0 1 0 1 0ns DELAY 148ns DELAY 296ns DELAY RESERVED
BLACK BURST LUMA DAC MR93 0 DISABLE 1 ENABLE
BLACK BURST Y DAC MR92 0 DISABLE 1 ENABLE
UNDERSHOOT LIMITER MR91 MR90 0 0 1 1 0 1 0 1 DISABLED -11 IRE -6 IRE -1.5 IRE
Figure 66. Mode Register 9 (MR9)
Chroma Delay Control (MR94-MR95) Timing Register Reset (TR07)
The Chroma signal can be delayed by up to 8 clock cycles at 27 MHz using MR94-95. For further information see also Chroma/Luma Delay Section.
TIMING REGISTER 0 (TR07-TR00) (Address (SR4-SR0) = 0AH)
Toggling TR07 from low to high and low again resets the internal timing counters. This bit should be toggled after power-up, reset or changing to a new timing mode.
TIMING REGISTER 1 (TR17-TR10) (Address (SR4-SR0) = 0BH)
Figure 67 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to.
TR0 BIT DESCRIPTION Master/Slave Control (TR00)
Timing Register 1 is a 8-bit-wide register. Figure 68 shows the various operations under the control of Timing Register 1. This register can be read from as well written to. This register can be used to adjust the width and position of the master mode timing signals.
TR1 BIT DESCRIPTION HSYNC Width (TR10-TR11)
This bit controls whether the ADV7192 is in master or slave mode.
Timing Mode Selection (TR01-TR02)
These bits control the timing mode of the ADV7192. These modes are described in more detail in the Video Timing Description section of the data sheet.
BLANK Input Control (TR03)
These bits adjust the HSYNC pulsewidth. TPCLK = one clock cycle at 27 MHz.
HSYNC to VSYNC Delay (TR13-TR12)
This bit controls whether the BLANK input is used to accept blank signals or whether blank signals are internally generated. Note: When this input pin is tied high (to 5 V), the input is disabled regardless of the register setting. It, therefore, should be tied low (to Ground) to allow control over the I2C register.
Luma Delay (TR04-TR05)
These bits adjust the position of the HSYNC output relative to the VSYNC output. TPCLK = one clock cycle at 27 MHz.
HSYNC to VSYNC Rising Edge Delay (TR14-TR15)
The luma signal can be delayed by up to 222 ns (or six clock cycles at 27 MHz) using TR04-TR05. For further information see Chroma/Luma Delay section.
Min Luminance Value (TR06)
When the ADV7192 is in Timing Mode 1, these bits adjust the position of the HSYNC output relative to the VSYNC output rising edge. TPCLK = one clock cycle at 27 MHz.
VSYNC Width (TR14-TR15)
This bit is used to control the minimum luma output value by the ADV7192 in 2x Oversampling mode and 4x Oversampling mode. When this bit is set to a Logic 1, the luma is limited to 7IRE below the blank level. When this bit is set to (0), the luma value can be as low as the sync bottom level.
When the ADV7192 is configured in Timing Mode 2, these bits adjust the VSYNC pulsewidth. TPCLK = one clock cycle at 27 MHz.
HSYNC to Pixel Data Adjust (TR16-TR17)
This enables the HSYNC to be adjusted with respect to the pixel data. This allows the Cr and Cb components to be swapped.
TR07 TIMING REGISTER RESET TR07
TR06
TR05
TR04
TR03 BLANK INPUT CONTROL TR03 0 ENABLE 1 DISABLE
TR02
TR01
TR00
MASTER / SLAVE CONTROL TR00 0 SLAVE TIMING 1 MASTER TIMING TIMING MODE SELECTION TR02 TR01 0 0 0 1 1 0 1 1 MODE 0 MODE 1 MODE 2 MODE 3
MIN LUMINANCE VALUE TR06 0 1 LUMA MIN = SYNC BOTTOM LUMA MIN = BLANK -7.5 IRE 0 0 1 1
LUMA DELAY TR05 TR04 0 1 0 1 0ns DELAY 74ns DELAY 148ns DELAY 222ns DELAY
Figure 67. Timing Register 0
-36-
REV. 0
ADV7192
TR17 TR16 TR15 TR14 TR13 TR12 TR11 TR10 HSYNC TO PIXEL DATA ADJUST TR17 TR16 0 0 1 1 0 1 0 1 0 1 2 3 TPCLK T PCLK TPCLK TPCLK HSYNC TO VSYNC RISING EDGE DELAY (MODE 1 ONLY) TR15 TR14 0 1 TC TB TB + 32 s HSYNC TO VSYNC DELAY TR13 TR12 0 0 1 1 0 1 0 1 TB 0 TPCLK 4 T PCLK 8 TPCLK 18 TPCLK 0 0 1 1 HSYNC WIDTH TR11 TR10 0 1 0 1 TA 1 TPCLK 4 T PCLK 16 TPCLK 128 TPCLK
VSYNC WIDTH (MODE 2 ONLY) TR15 TR14 0 0 1 1 0 1 0 1 1 TPCLK 4 T PCLK 16 TPCLK 128 TPCLK
TIMING MODE 1 (MASTER/PAL)
LINE 1 HSYNC TA TB VSYNC TC LINE 313 LINE 314
Figure 68. Timing Register 1
This adjustment is available in both master and slave timing modes. TPCLK = one clock cycle at 27 MHz.
SUBCARRIER FREQUENCY REGISTERS 3-0 (FSC31-FSC0) (Address (SR4-SR0) = 0CH-0FH)
SUBCARRIER PHASE REGISTER
FPH7
FPH6
FPH5
FPH4
FPH3
FPH2
FPH1
FPH0
Figure 70. Subcarrier Phase Register
CLOSED CAPTIONING EVEN FIELD DATA REGISTER 1-0 (CCD15-CCD0) (Address (SR4-SR0) = 11-12H)
These 8-bit-wide registers are used to set up the Subcarrier Frequency. The value of these registers are calculated by using the following equation:
Subcarrier Frequency Register =
(2
32
- 1 x f SCF fCLK
BYTE 1 CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD8
)
These 8-bit-wide registers are used to set up the closed captioning extended data bytes on Even Fields. Figure 71 shows how the high and low bytes are set up in the registers.
Example: NTSC Mode, fCLK = 27 MHz, fSCF = 3.5795454 MHz
Subcarrier Frequency Value =
BYTE 0
CCD7
CCD6
CCD5
CCD4
CCD3
CCD2
CCD1
CCD0
(2
32
- 1 x 3.5795454 x 106 27 x 10
6
)
Figure 71. Closed Captioning Extended Data Register
CLOSED CAPTIONING ODD FIELD DATA REGISTER 1-0 (CED15-CED0) (Subaddress (SR4-SR0) = 13-14H)
Subcarrier Register Value = 21F07C16 Hex Figure 69 shows how the frequency is set up by the four registers.
SUBCARRIER FREQUENCY REG 3 SUBCARRIER FREQUENCY REG 2 SUBCARRIER FREQUENCY REG 1 SUBCARRIER FREQUENCY REG 0 FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
These 8-bit-wide registers are used to set up the closed captioning data bytes on Odd Fields. Figure 72 shows how the high and low bytes are set up in the registers.
BYTE 1 CED15 CED14 CED13 CED12 CED11 CED10 CED9 CED8
FSC23
FSC22
FSC21
FSC20
FSC19
FSC18
FSC17
FSC16
FSC15
FSC14
FSC13
FSC12
FSC11
FSC10
FSC9
FSC8
BYTE 0 CED7 CED6 CED5 CED4 CED3 CED2 CED1 CED0
FSC7
FSC6
FSC5
FSC4
FSC3
FSC2
FSC1
FSC0
Figure 72. Closed Captioning Data Register
NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3-0 (PCE15-0, PCO15-0)/(TXE15-0, TXO15-0) (Subaddress (SR4-SR0) = 15-18H)
Figure 69. Subcarrier Frequency Registers
SUBCARRIER PHASE REGISTER (FPH7-FPH0) (Address (SR4-SR0) = 10H)
This 8-bit-wide register is used to set up the Subcarrier Phase. Each bit represents 1.41. For normal operation this register is set to 00Hex.
These 8-bit-wide registers are used to enable the NTSC pedestal/ PAL Teletext on a line-by-line basis in the vertical blanking interval for both odd and even fields. Figures 73 and 74 show the four control registers. A Logic 1 in any of the bits of these
REV. 0
-37-
ADV7192
registers has the effect of turning the Pedestal OFF on the equivalent line when used in NTSC. A Logic 1 in any of the bits of these registers has the effect of turning Teletext ON on the equivalent line when used in PAL.
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
TC07
TC06
TC05
TC04
TC03
TC02
TC01
TC00
FIELD 1/3
PCO7
PCO6
PCO5
PCO4
PCO3
PCO2
PCO1
PCO0
TTXREQ RISING EDGE CONTROL TC07 TC06 TC05 TC04 0 0 0 0 0 PCLK 0 0 0 1 1 PCLK '' '' '' '' '' PCLK 1 1 1 0 14 PCLK 1 1 1 1 15 PCLK
TTXREQ FALLING EDGE CONTROL TC03 TC02 TC01 TC00 0 0 0 0 0 PCLK 0 0 0 1 1 PCLK '' '' '' '' '' PCLK 1 1 1 0 14 PCLK 1 1 1 1 15 PCLK
LINE 25 LINE 24 LINE 23
LINE 22 LINE 21 LINE 20
LINE 19 LINE 18
FIELD 1/3
PCO15 PCO14 PCO13
LINE 17 LINE 16
PCO12 PCO11 PCO10
PCO9
PCO8
Figure 75. Teletext Control Register
CGMS_WSS REGISTER 0 C/W0 (C/W07-C/W00) (Address (SR4-SR0) = 19H)
LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
FIELD 2/4
PCE7
PCE6
PCE5
PCE4
PCE3
PCE2
PCE1
PCE0
LINE 25 LINE 24 LINE 23
LINE 22 LINE 21 LINE 20
LINE 19 LINE 18
FIELD 2/4
PCE15
PCE14
PCE13
PCE12
PCE11
PCE10
PCE9
PCE8
CGMS_WSS register 0 is an 8-bit-wide register. Figure 76 shows the operations under control of this register.
C/W0 BIT DESCRIPTION CGMS Data Bits (C/W00-C/W03)
Figure 73. Pedestal Control Registers
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9 LINE 8 LINE 7
FIELD 1/3
TXO7
TXO6
TXO5
TXO4
TXO3
TXO2
TXO1
TXO0
LINE 22 LINE 21 LINE 20
LINE 19 LINE 18 LINE 17
LINE 16 LINE 15
These four data bits are the final four bits of CGMS data output stream. Note it is CGMS data ONLY in these bit positions, i.e., WSS data does not share this location.
CGMS CRC Check Control (C/W04)
FIELD 1/3
TXO15
TXO14
TXO13
TXO12
TXO11
TXO10
LINE 9
TXO9
LINE 8
TXO8
LINE 7
LINE 14 LINE 13
LINE 12 LINE 11 LINE 10
FIELD 2/4
TXE7
TXE6
TXE5
TXE4
TXE3
TXE2
TXE1
TXE0
LINE 22 LINE 21 LINE 20
LINE 19 LINE 18 LINE 17
LINE 16 LINE 15
When this bit is enabled (1), the last six bits of the CGMS data, i.e., the CRC check sequence, is internally calculated by the ADV7192. If this bit is disabled (0) the CRC values in the register are output to the CGMS data stream.
CGMS Odd Field Control (C/W05)
FIELD 2/4
TXE15
TXE14
TXE13
TXE12
TXE11
TXE10
TXE9
TXE8
Figure 74. Teletext Control Registers
TELETEXT REQUEST CONTROL REGISTER TC07 (TC07-TC00) (Address (SR4-SR0) = 1CH)
When this bit is set (1), CGMS is enabled for odd fields. Note this is only valid in NTSC mode.
CGMS Even Field Control (C/W06)
Teletext Control Register is an 8-bit-wide register. See Figure 75.
TTXREQ Falling Edge Control (TC00-TC03)
When this bit is set (1), CGMS is enabled for even fields. Note this is only valid in NTSC mode.
WSS Control (C/W07)
These bits control the position of the falling edge of TTXREQ. It can be programmed from zero clock cycles to a maximum of 15 clock cycles. This controls the active window for Teletext data. Increasing this value reduces the amount of Teletext bits below the default of 360. If Bits TC00-TC03 are 00Hex when Bits TC04- TC07 are changed then the falling edge of TTREQ will track that of the rising edge (i.e., the time between the falling and rising edge remains constant). PCLK = clock cycle at 27 MHz.
TTXREQ Rising Edge Control (TC04-TC07)
When this bit is set (1), wide screen signalling is enabled. Note this is only valid in PAL mode.
CGMS_WSS REGISTER 1 C/W1 (C/W17-C/W10) (Address (SR4-SR0) = 1AH)
CGMS_WSS register 1 is an 8-bit-wide register. Figure 77 shows the operations under control of this register.
C/W1 BIT DESCRIPTION CGMS/WSS Data (C/W10-C/W15)
These bits control the position of the rising edge of TTXREQ. It can be programmed from zero clock cycles to a maximum of 15 clock cycles. PCLK = clock cycle at 27 MHz.
C/W07 C/W06 C/W05 CGMS ODD FIELD CONTROL C/W05 0 1 DISABLE ENABLE C/W04
These bit locations are shared by CGMS data and WSS data. In NTSC mode these bits are CGMS data. In PAL mode these bits are WSS data.
C/W03
C/W02
C/W01
C/W00
WSS CONTROL C/W07 0 1 DISABLE ENABLE
C/W03 - C/W00 CGMS DATA BITS
CGMS EVEN FIELD CONTROL C/W06 0 1 DISABLE ENABLE
CGMS CRC CHECK CONTROL C/W04 0 1 DISABLE ENABLE
Figure 76. CGMS_WSS Register 0
-38-
REV. 0
ADV7192
CGMS Data (C/W16-C/W17)
These bits are CGMS data bits only.
C/W17 C/W16 C/W15 C/W14 C/W13 C/W12 C/W11 C/W10
COLOR CONTROL REGISTERS 1-2 (CC1-CC2) (Address (SR4-SR0) = 1EH-1FH)
The color control registers are 8-bit-wide registers used to scale the U and V output levels. Figure 75 shows the operations under control of these registers.
CC17 CC16 CC15 CC14 CC13 CC12 CC11 CC10
C/W17 - C/W16 CGMS DATA
C/W15 - C/W10 CGMS/WSS DATA
Figure 77. CGMS_WSS Register 1
CGMS_WSS REGISTER 2 C/W1 (C/W27-C/W20) (Address (SR4-SR0) = 1BH)
CC17 - CC10 U SCALE VALUE
CC27
CC26
CC25
CC24
CC23
CC22
CC21
CC20
CGMS_WSS Register 2 is an 8-bit-wide register. Figure 78 shows the operations under control of this register.
C/W2 BIT DESCRIPTION CGMS/WSS Data (C/W20-C/W27)
CC27 - CC20 V SCALE VALUE
Figure 80. Color Control Registers
CC1 BIT DESCRIPTION U Scale Value (CC10-CC17)
These bit locations are shared by CGMS data and WSS data. In NTSC mode these bits are CGMS data. In PAL mode these bits are WSS data.
C/W27 C/W26 C/W25 C/W24 C/W23 C/W22 C/W21 C/W20
These eight bits represent the value required to scale the U level from 0.0 to 2.0 of its initial level. The value of these eight bits is calculated using the following equation: U Scale Value = Scale Factor x 128 Example: Scale Factor = 1.18 U Scale Value = 1.18 x 128 = 151.04 U Scale Value = 151 (rounded to the nearest integer) U Scale Value = 10010111b U Scale Value = 97h
CC2 BIT DESCRIPTION V Scale Value (CC20-CC27)
C/W27 - C/W20 CGMS/WSS DATA
Figure 78. CGMS_WSS Register 2
CONTRAST CONTROL REGISTER (CC00-CC07) (Address (SR4-SR0) = 1DH)
The contrast control register is an 8-bit-wide register used to scale the Y output levels. Figure 79 shows the operation under control of this register.
Y Scale Value (CC00-CC07)
These eight bits represent the value required to scale the Y pixel data from 0.0 to 1.5 of its initial level. The value of these eight bits is calculated using the following equation: Y Scale Value = Scale Factor x 128 Example: Scale Factor = 1.18 Y Scale Value = 1.18 x 128 = 151.04 Y Scale Value = 151 (rounded to the nearest integer) Y Scale Value = 10010111b Y Scale Value = 97h
CC07 CC06 CC05 CC04 CC03 CC02 CC01 CC00
These eight bits represent the value required to scale the V pixel data from 0.0 to 2.0 of its initial level. The value of these eight bits is calculated using the following equation: V Scale Value = Scale Factor x 128 Example: Scale Factor = 1.18 V Scale Value = 1.18 x 128 = 151.04 V Scale Value = 151 (rounded to the nearest integer) V Scale Value = 10010111b V Scale Value = 97h
CC07 - CC00 Y SCALE VALUE
Figure 79. Contrast Control Register
REV. 0
-39-
ADV7192
HUE ADJUST CONTROL REGISTER (HCR) (Address (SR5-SR0) = 20H) BRIGHTNESS CONTROL REGISTER (BCR) (Address (SR5-SR0) = 21H)
The hue control register is an 8-bit-wide register used to adjust the hue on the composite and chroma outputs. Figure 81 shows the operation under control of this register.
HCR7 HCR6 HCR5 HCR4 HCR3 HCR2 HCR1 HCR0
The brightness control register is an 8-bit-wide register which allows brightness control. Figure 82 shows the operation under control of this register.
BCR BIT DESCRIPTION Brightness Value (BCR0-BCR6)
HCR7 - HCR0 HUE ADJUST VALUE
Figure 81. Hue Control Register
HCR BIT DESCRIPTION Hue Adjust Value (HCR0-HCR7)
Seven bits of this 8-bit-wide register are used to control the brightness level. The brightness is controlled by adding a programmable setup level onto the scaled Y data. This brightness level can be a positive or negative value. The programmable brightness levels in NTSC, without pedestal, and PAL are max 15 IRE and min -7.5 IRE, in NTSC pedestal max 22.5 IRE and min 0 IRE.
Table IV. Brightness Control Register Value
These eight bits represent the value required to vary the hue of the video data, i.e., the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the colorburst. The ADV7192 provides a range of 22.5 increments of 0.17578125. For normal operation (zero adjustment), this register is set to 80Hex. FFHex and 00Hex represent the upper and lower limit (respectively) of adjustment attainable. Hue Adjust [] = 0.17578125 x (HCRd - 128); for positive Hue Adjust Value Example: To adjust the hue by 4 write 97h to the Hue Adjust Control Register: (4/0.17578125) + 128 = 151d* = 97h To adjust the hue by (-4) write 69h to the Hue Adjust Control Register: (-4/0.17578125) + 128 = 105d* = 69h
*Rounded to the nearest integer.
Setup Level in NTSC with Pedestal 22.5 IRE 15 IRE 7.5 IRE 0 IRE
Setup Level in NTSC No Pedestal 15 IRE 7.5 IRE 0 IRE -7.5 IRE
Setup Level in PAL 15 IRE 7.5 IRE 0 IRE -7.5 IRE
Brightness Control Register Value 1Eh 0Fh 00h 71h
NOTE Values in the range from 3F h to 44h might result in an invalid output signal.
EXAMPLE
1. Standard: NTSC with Pedestal. To add 20 IRE brightness level write 28h into the Brightness Control Register: [Brightness Control Register Value]h = [IRE Value 2.015631]h = [20 2.015631]h = [40.31262]h = 28h
2. Standard: PAL. To add -7 IRE brightness level write 72h into the Brightness Control Register: [|IRE Value| 2.015631] = [7 2.015631] = [14.109417] = 0001110b [0001110] into two's complement = 1110010b = 72h
NTSC WITHOUT PEDESTAL +7.5 IRE 100 IRE
0 IRE NO SETUP VALUE ADDED POSITIVE SETUP VALUE ADDED WRITE TO BRIGHTNESS CONTROL REGISTER: 12h BCR5 BCR4 BCR3 BCR6 - BCR0 BRIGHTNESS VALUE NEGATIVE SETUP VALUE ADDED WRITE TO BRIGHTNESS CONTROL REGISTER: 6Eh BCR2 BCR1 BCR0
-7.5 IRE
BCR7 BCR7
BCR6
ZERO MUST BE WRITTEN TO THIS BIT
Figure 82. Brightness Control Register
-40-
REV. 0
ADV7192
SHARPNESS RESPONSE REGISTER (PR) (Address (SR5-SR0) = 22H)
DNR07 DNR06 DNR05 DNR04 DNR03 DNR02 DNR01 DNR00
The sharpness response register is an 8-bit-wide register. The four MSBs are set to 0. The four LSBs are written to in order to select a desired filter response. Figure 83 shows the operation under control of this register.
PR BIT DESCRIPTION Sharpness Response Value (PR3-PR0)
CORING GAIN DATA DNR DNR DNR DNR 07 06 05 04 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 +1/16 +2/16 +3/16 +4/16 +5/16 +6/16 +7/16 +8/16
CORING GAIN BORDER DNR DNR DNR DNR 03 02 01 00 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 +1/16 +2/16 +3/16 +4/16 +5/16 +6/16 +7/16 +8/16
These four bits are used to select the desired luma filter response. The option of twelve responses is given supporting a gain boost/ attenuation in the range -4 dB to +4 dB. The value 12 (1100) written to these four bits corresponds to a boost of +4 dB while the value 0 (0000) corresponds to -4 dB. For normal operation these four bits are set to 6 (0110). Note: Luma Filter Select has to be set to Extended Mode and Sharpness Filter Control has to be enabled for settings in the Sharpness Control Register to take effect (MR02-04 = 100; MR74 = 1).
Reserved (PR4-PR7)
Figure 84. DNR Register 0 in DNR Sharpness Mode
DNR07 DNR06 DNR05 DNR04 DNR03 DNR02 DNR01 DNR00
CORING GAIN DATA DNR DNR DNR DNR 07 06 05 04 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 -1/8 -2/8 -3/8 -4/8 -5/8 -6/8 -7/8 -1
CORING GAIN BORDER DNR DNR DNR DNR 03 02 01 00 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 -1/8 -2/8 -3/8 -4/8 -5/8 -6/8 -7/8 -1
A Logical 0 must be written to these bits.
PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0
PR7 - PR4 ZERO MUST BE WRITTEN TO THESE BITS
PR3 - PR0 SHARPNESS RESPONSE VALUE
Figure 85. DNR Register 0 in DNR Mode
DNR1 BIT DESCRIPTION DNR Threshold (DNR10-DNR15)
Figure 83. Sharpness Response Register
DNR REGISTERS 2-0 (DNR2-DNR0) (Address (SR5-SR0) = 23H-25H)
These six bits are used to define the threshold value in the range of 0 to 63. The range is an absolute value.
Border Area (DNR16)
The Digital Noise Reduction Registers are three 8-bit-wide register. They are used to control the DNR processing. See Digital Noise Register section.
Coring Gain Border (DNR00-DNR03)
These four bits are assigned to the gain factor applied to border areas. In DNR Mode the range of gain values is 0-1, in increments of 1/8. This factor is applied to the DNR filter output which lies below the set threshold range. The result is then subtracted from the original signal. In DNR Sharpness Mode the range of gain values is 0-0.5, in increments of 1/16. This factor is applied to the DNR filter output which lies above the threshold range. The result is added to the original signal.
Coring Gain Data (DNR04-DNR07)
In setting DNR16 to a Logic 1 the block transition area can be defined to consist of four pixels. If this bit is set to a Logic 0 the border transition area consists of two pixels, where one pixel refers to two clock cycles at 27 MHz.
Block Size Control (DNR17)
This bit is used to select the size of the data blocks to be processed (see Figure 86). Setting the block size control function to a Logic 1 defines a 16 x 16 pixel data block, a Logic 0 defines an 8 x 8 pixel data block, where one pixel refers to two clock cycles at 27 MHz.
720 485 PIXELS (NTSC) 2 PIXEL BORDER DATA
These four bits are assigned to the gain factor applied to the luma data inside the MPEG pixel block. In DNR Mode the range of gain values is 0-1, in increments of 1/8. This factor is applied to the DNR filter output which lies below the set threshold range. The result is then subtracted from the original signal. In DNR Sharpness Mode the range of gain values is 0-0.5, in increments of 1/16. This factor is applied to the DNR filter output which lies above the threshold range. The result is added to the original signal. Figures 84 and 85 show the various operations under the control of DNR Register 0. REV. 0 -41-
88 88 PIXEL BLOCK PIXEL BLOCK
Figure 86. MPEG Block Diagram
ADV7192
DNR17 DNR16 DNR15 DNR14 DNR13 DNR12 DNR11 DNR10
BLOCK SIZE CONTROL DNR17 0 1 8 PIXELS 16 PIXELS
BORDER AREA DNR16 0 1 2 PIXELS 4 PIXELS
DNR THRESHOLD DNR DNR DNR DNR DNR DNR 15 14 13 12 11 10 0 0 * * * 1 1 0 0 * * * 1 1 0 0 * * * 1 1 0 0 * * * 1 1 0 0 * * * 1 1 0 1 * * * 0 1 0 1 * * * 62 63
Figure 87. DNR Register 1
DNR2 BIT DESCRIPTION DNR Input Select (DNR20-DNR22)
Three bits are assigned to select the filter which is applied to the incoming Y data. The signal which lies in the passband of the selected filter is the signal which will be DNR processed. Figure 88 shows the filter responses selectable with this control.
DNR Mode Control (DNR23)
DNR MODE
GAIN CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN CORING GAIN DATA CORING GAIN BORDER SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL
NOISE SIGNAL PATH FILTER BLOCK FILTER OUTPUT < THRESHOLD ? FILTER OUTPUT > THRESHOLD MAIN SIGNAL PATH
This bit controls the DNR mode selected. A Logic 0 selects DNR mode, a Logic 1 selects DNR Sharpness mode. DNR works on the principle of defining low amplitude, highfrequency signals as probable noise and subtracting this noise from the original signal. In DNR mode, it is possible to subtract a fraction of the signal which lies below the set threshold, assumed to be noise, from the original signal. The threshold is set in DNR Register 1. When DNR Sharpness mode is enabled it is possible to add a fraction of the signal which lies above the set threshold to the original signal, since this data is assumed to be valid data and not noise. The overall effect being that the signal will be boosted (similar to using Extended SSAF Filter).
1 FILTER D 0.8
Y DATA INPUT
DNR OUT
DNR SHARPNESS MODE
GAIN CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN CORING GAIN DATA CORING GAIN BORDER ADD SIGNAL ABOVE THRESHOLD RANGE TO ORIGINAL SIGNAL DNR OUT
NOISE SIGNAL PATH FILTER BLOCK FILTER OUTPUT > THRESHOLD ? FILTER OUTPUT < THRESHOLD MAIN SIGNAL PATH
Y DATA INPUT
MAGNITUDE - dB
0.6
FILTER C
Figure 89. Block Diagram for DNR Mode and DNR Sharpness Mode
FILTER B
0.4
Block Offset (DNR24-DNR27)
0.2
FILTER A
0
0
1
2
3 4 FREQUENCY - MHz
5
6
Four bits are assigned to this control which allows a shift of the data block of 15 pixels maximum. Consider the coring gain positions fixed. The block offset shifts the data in steps of one pixel such that the border coring gain factors can be applied at the same position regardless of variations in input timing of the data.
APPLY DATA CORING GAIN APPLY BORDER CORING GAIN
Figure 88. Filter Response of Filters Selectable
OXXXXXXO OXXXXXXO
DNR27-DNR24 = 01HEX
OXXXXXXO OXXXXXXO OXXXXXXO OXXXXXXO
OFFSET CAUSED BY VARIATIONS IN INPUT TIMING
Figure 90. DNR27-DNR24 Block Offset Control
-42-
REV. 0
ADV7192
DNR27 DNR26 DNR25 DNR24 DNR23 DNR22 DNR21 DNR20
BLOCK OFFSET CONTROL DNR DNR DNR DNR 27 26 25 24 0 0 0 * * * 1 1 1 0 0 0 * * * 1 1 1 0 0 1 * * * 0 1 1 0 1 0 * * * 1 0 1 0 PIXEL OFFSET 1 PIXEL OFFSET 2 PIXEL OFFSET * * * 13 PIXEL OFFSET 14 PIXEL OFFSET 15 PIXEL OFFSET
DNR MODE CONTROL DNR23 0 DNR MODE 1 DNR SHARPNESS MODE
DNR INPUT SELECT CONTROL DNR DNR DNR 22 21 20 0 0 0 1 0 1 1 0 1 0 1 0 FILTER A FILTER B FILTER C FILTER D
Figure 91. DNR Register 2
GAMMA CORRECTION REGISTERS 0-13 (GAMMA CORRECTION 0-13) (Address (SR5-SR0) = 26H-32H)
y96 = [(80/224)0.5 x 224] + 16 = 150* y128 = [(112/224)0.5 x 224] + 16 = 174*
*Rounded to the nearest integer.
The Gamma Correction Registers are fourteen 8-bit wide register. They are used to program the gamma correction Curves A and B. Generally gamma correction is applied to compensate for the nonlinear relationship between signal input and brightness level output (as perceived on the CRT). It can also be applied wherever nonlinear processing is used. Gamma correction uses the function: SignalOUT = (SignalIN) where = gamma power factor Gamma correction is performed on the luma data only. The user has the choice to use two different curves, Curve A or Curve B. At any one time only one of these curves can be used. The response of the curve is programmed at seven predefined locations. In changing the values at these locations the gamma curve can be modified. Between these points linear interpolation is used to generate intermediate values. Considering the curve to have a total length of 256 points, the seven locations are at: 32, 64, 96, 128, 160, 192, and 224. Location 0, 16, 240 and 255 are fixed and can not be changed. For the length of 16 to 240 the gamma correction curve has to be calculated as below: y = x where y = gamma corrected output x = linear input signal = gamma power factor To program the gamma correction registers, the seven values for y have to be calculated using the following formula: yn = [x(n-16) /(240-16) ] x (240-16) + 16 where x(n-16) = Value for x along x-axis at points n = 32, 64, 96, 128, 160, 192, or 224 yn = Value for y along the y-axis, which has to be written into the gamma correction register
0.5
The above will result in a gamma curve shown below, assuming a ramp signal as an input.
300 GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT
GAMMA-CORRECTED AMPLITUDE
250 300 SIGNAL OUTPUT 200 250 0.5 150 200 150 100 100 50 50 0 SIGNAL INPUT
0
50
100
150 LOCATION
200
250
Figure 92. Signal Input (Ramp) and Signal Output for Gamma 0.5
300 GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT FOR VARIOUS GAMMA VALUES
GAMMA-CORRECTED AMPLITUDE
250 SIGNAL OUTPUTS 200 0.3 0.5 150
UT NP LI 1.5 NA G SI
100
1.8
50
0
0
50
100
150 LOCATION
200
250
Figure 93. Signal Input (Ramp) and Selectable Gamma Output Curves
Example: y32 = [(16/224) x 224] + 16 = 76* y64 = [(48/224)0.5 x 224] + 16 = 120* REV. 0
The gamma curves shown above are examples only, any user defined curve is acceptable in the range of 16-240.
-43-
ADV7192
BRIGHTNESS DETECT REGISTER (Address (SR5-SR0) = 34H) OCR BIT DESCRIPTION Reserved (OCR00)
The Brightness Detect Register is an 8-bit-wide register used only to read back data in order to monitor the brightness/darkness of the incoming video data on a field-by-field basis. The brightness information is read from the I2C and based on this information, the color controls or the gamma correction controls may be adjusted. The luma data is monitored in the active video area only. The average brightness I2C register is updated on the falling edge of every VSYNC signal.
OUTPUT CLOCK REGISTER (OCR 9-0) (Address (SR4-SR0) = 35H)
A Logic 0 must be written to this bit.
CLKOUT Pin Control (OCR01)
This bit enables the CLKOUT pin when set to 1 and, therefore, outputs a 54 MHz clock generated by the internal PLL. The PLL and 4x Oversampling have to be enabled for this control to take effect, (MR61 = 0; MR16 = 1).
Reserved (OCR02-03)
A Logic 0 must be written to this bit.
Reserved (OCR04-06)
A Logic 1 must be written to these bits.
Reserved (OCR07)
The Output Clock Register is an 8-bit-wide register. Figure 93 shows the various operations under the control of this register.
A Logic 0 must be written to this bit.
OCR07
OCR06
OCR05
OCR04
OCR03
OCR02
OCR01
OCR00
OCR07 ZERO MUST BE WRITTEN TO THIS BIT
OCR06 - OCR04 ONE MUST BE WRITTEN TO THESE BITS
OCR03 - OCR02 ZERO MUST BE WRITTEN TO THESE BITS
OCR00 ZERO MUST BE WRITTEN TO THIS BIT CLKOUT PIN CONTROL OCR01 0 ENSABLED 1 DISABLED
Figure 94. Output Clock Register
-44-
REV. 0
ADV7192
APPENDIX 1
BOARD DESIGN AND LAYOUT CONSIDERATIONS
The ADV7192 is a highly integrated circuit containing both precision analog and high-speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high-speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system level design such that high-speed, accurate performance is achieved. The Recommended Analog Circuit Layout shows the analog interface between the device and monitor. The layout should be optimized for lowest noise on the ADV7192 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and GND pins should by minimized so as to minimize inductive ringing.
Ground Planes
pins on the ADV7192 must have at least one 0.1 F decoupling capacitor to GND. These capacitors should be placed as close as possible to the device. It is important to note that while the ADV7192 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three-terminal voltage regulator for supplying power to the analog power plane.
Digital Signal Interconnect
The digital inputs to the ADV7192 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV7192 should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC), and not the analog power plane.
Analog Signal Interconnect
The ground plane should encompass all ADV7192 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7192, the analog output traces, and all the digital signal traces leading up to the ADV7192. This should be as substantial as possible to maximize heat spreading and power dissipation on the board.
Power Planes
The ADV7192 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (VAA). This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead. This bead should be located within three inches of the ADV7192. The metallization gap separating device power plane and board power plane should be as narrow as possible to minimize the obstruction to the flow of heat from the device into the general board. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7192 power pins and voltage reference circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common-mode.
Supply Decoupling
The ADV7192 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection. Digital inputs, especially pixel data inputs and clocking signals should never overlay any of the analog signal circuitry and should be kept as far away as possible. For best performance, the outputs should each have a 300 load resistor connected to GND. These resistors should be placed as close as possible to the ADV7192 so as to minimize reflections. The ADV7192 should have no inputs left floating. Any inputs that are not required should be tied to ground.
For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Best performance is obtained with 0.1 F ceramic capacitor decoupling. Each group of VAA
REV. 0
-45-
ADV7192
POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP 5V (VAA) 10 F 5V (VAA) 5V (VAA) 5V (VDD) 0.1 F COMP2 VREF Cb0 - Cb9 Cr0 - Cr9 DAC B 0.1 F COMP1 53, 48, 38 VAA 79, 68, 34, 21 VDD DAC A 300 10 F 0.1 F 0.1 F
ADV7192
DAC C
300
Y0/P8 - Y7/P15 Y8 - Y9 UNUSED INPUTS SHOULD BE GROUNDED P7 - P0
300 DAC D CSO_HSO VSO/TTX/CLAMP PAL_NTSC SCRESET/RTC/TR HSYNC DAC F 300 100 SCL 100 SDATA TTXREQ CLKIN ALSB 5V (VAA) 4.7k AGND DGND 80, 69, 43, 33, 22 RSET2 RSET1 1.2k 52, 49, 35 1.2k MPU BUS DAC E 300 5V (VAA) 5k 5V (VAA) 5k 300
5V (VAA) 4.7k 4.7 F 6.3V 27MHz CLOCK (SAME CLOCK AS USED BY MPEG2 DECODER)
VSYNC BLANK RESET
Figure 95. Recommended Analog Circuit Layout
-46-
REV. 0
ADV7192
APPENDIX 2
CLOSED CAPTIONING
The ADV7192 supports closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of even fields. Closed captioning consists of a seven-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run-in signal, the blanking level is held for two data bits and is followed by a Logic Level 1 start bit. Sixteen bits of data follow the start bit. These consist of two eight-bit bytes, seven data bits, and one odd parity bit. The data for these bytes is stored in Closed Captioning Data Registers 0 and 1. The ADV7192 also supports the extended closed captioning operation which is active during even fields and is encoded on Scan Line 284. The data for this operation is stored in Closed Captioning Extended Data Registers 0 and 1. All clock run-in signals and timing to support Closed Captioning on Lines 21 and 284 are generated automatically by the ADV7192 All pixels inputs are ignored during Lines 21 and 284 if closed captioning is enabled.
FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA608 describe the closed captioning information for Lines 21 and 284. The ADV7192 uses a single buffering method. This means that the closed captioning buffer is only one byte deep, therefore, there will be no frame delay in outputting the closed captioning data unlike other two byte deep buffering systems. The data must be loaded one line before (Line 20 or Line 283) it is outputted on Line 21 and Line 284. A typical implementation of this method is to use VSYNC to interrupt a microprocessor, which in turn will load the new data (two bytes) every field. If no new data is required for transmission, 0s must be inserted in both data registers, this is called NULLING. It is also important to load control codes all of which are double bytes on Line 21 or a TV will not recognize them. If there is a message like Hello World which has an odd number of characters, it is important to pad it out to even in order to get end of caption 2-byte control code to land in the same field.
10.5
0.25 s
12.91 s 7 CYCLES OF 0.5035 MHz (CLOCK RUN-IN) S T A R T TWO 7-BIT + PARITY ASCII CHARACTERS (DATA) P A R I T Y P A R I T Y
D0-D6
50 IRE
D0-D6
BYTE 0 40 IRE REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003 s 27.382 s 33.764 s
BYTE 1
Figure 96. Closed Captioning Waveform (NTSC)
REV. 0
-47-
ADV7192
APPENDIX 3
COPY GENERATION MANAGEMENT SYSTEM (CGMS)
The ADV7192 supports Copy Generation Management System (CGMS) conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control whether or not CGMS data is outputed on ODD and EVEN fields. CGMS data can only be transmitted when the ADV7192 is configured in NTSC mode. The CGMS data is 20 bits long, the function of each of these bits is as shown below. The CGMS data is preceded by a reference pulse of the same amplitude and duration as a CGMS bit, see Figure 96. These bits are outputed from the configuration registers in the following order: C/W00 = C16, C/W01 = C17, C/W02 = C18, C/W03 = C19, C/W10 = C8, C/W11 = C9, C/W12 = C10, C/W13 = C11, C/W14 = C12, C/W15 = C13, C/W16 = C14, C/W17 = C15, C/W20 = C0, C/W21 = C1, C/W22 = C2, C/W23 = C3, C/W24 = C4, C/W25 = C5, C/W26 = C6, C/W27 = C7. If the bit C/W04 is set to a Logic 1, the last six bits C19-C14 which comprise the 6-bit CRC check sequence are calculated automatically on the ADV7192 based on the lower 14 bits (C0-C13) of the data in the data registers and output with the remaining 14-bits to form the complete 20-bits of the CGMS data. The calculation of the CRC sequence is based on the polynomial X6 + X + 1 with a preset value of 111111. If C/W04 is set to a Logic 0 then all 20-bits (C0-C19) are output directly from the CGMS registers (no CRC calculated, must be calculated by the user).
Function of CGMS Bits
Word 0 - 6 Bits Word 1 - 4 Bits Word 2 - 6 Bits CRC - 6 Bits CRC Polynomial = X6 + X + 1 (Preset to 111111) WORD 0 B1 B2 B3 WORD 0 B4, B5, B6 WORD 1 B7, B8, B9, B10 WORD 2 B11, B12, B13, B14 1 16:9 Letterbox 0 4:3 Normal
Aspect Ratio Display Format Undefined
Identification Information About Video and Other Signals (e.g., Audio) Identification Signal Incidental to Word 0
Identification Signal and Information Incidental to Word 0
100 IRE REF 70 IRE C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 CRC SEQUENCE
0 IRE 49.1 s -40 IRE 11.2 s 2.235 s 20ns 0.5 s
Figure 97. CGMS Waveform Diagram
-48-
REV. 0
ADV7192
APPENDIX 4
WIDE SCREEN SIGNALING
The ADV7192 supports Wide Screen Signaling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7192 is configured in PAL mode. The WSS data is 14-bits long, the function of each of these bits is as shown below. The WSS data is preceded by a run-in sequence and a Start Code, see Figure 97. The bits are output from the configuration registers in the following order: C/W20 = W0, C/W21 = W1, C/W22 = W2, C/W23 = W3, C/W24 = W4, C/W25 = W5, C/W26 = W6, C/W27 = W7, C/W10 = W8, C/W11 = W9, C/W12 = W10, C/W13 = W11, C/W14 = W12, C/W15 = W13. If the bit C/W07 is set to a Logic 1, it enables the WSS data to be transmitted on Line 23. The latter portion of Line 23 (42.5 s from the falling edge of HSYNC) is available for the insertion of video.
Function of CGMS Bits
B4 0 1 B5 0 1 B6 0 1 B7 B9 0 1 0 1
Camera Mode Film Mode Standard Coding Motion Adaptive Color Plus No Helper Modulated Helper RESERVED B10 0 0 1 1 No Open Subtitles Subtitles in Active Image Area Subtitles Out of Active Image Area RESERVED
Bit 0-Bit 2 Bit 3 B0, 0 1 0 1 0 1 0 1 B1, 0 0 1 1 0 0 1 1 B2, 0 0 0 0 1 1 1 1
Aspect Ratio/Format/Position Is Odd Parity Check of Bit 0-Bit 2 B3 1 0 0 1 0 1 1 0 Aspect Ratio 4:3 14:9 14:9 16:9 16:9 >16:9 14:9 16:9 Format Format Full Format Letterbox Letterbox Letterbox Letterbox Letterbox Full Format Nonapplicable Position Position Nonapplicable Center Top Center Top Center Center Nonapplicable
B11 0 No Surround Sound Information 1 Surround Sound Mode B12 RESERVED B13 RESERVED
500mV W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 RUN-IN SEQUENCE START CODE ACTIVE VIDEO
11.0 s 38.4 s 42.5 s
Figure 98. WSS Waveform Diagram
REV. 0
-49-
ADV7192
APPENDIX 5
TELETEXT INSERTION
Time, tPD, is the time needed by the ADV7192 to interpolate input data on TTX and insert it onto the CVBS or Y outputs, such that it appears tSYNTXTOUT = 10.2 s after the leading edge of the horizontal signal. Time TXTDEL is the pipeline delay time by the source that is gated by the TTREQ signal in order to deliver TTX data. With the programmability that is offered with TTXREQ signal on the Rising/Falling edges, the TTX data is always inserted at the correct position of 10.2 s after the leading edge of Horizontal Sync pulse, thus this enables a source interface with variable pipeline delays. The width of the TTXREQ signal must always be maintained such that it allows the insertion of 360 (in order to comply with the Teletext Standard PAL-WST) teletext bits at a text data rate of 6.9375 Mbits/s, this is achieved by setting TC03-TC00 to 0. The insertion window is not open if the Teletext Enable bit (MR34) is set to 0.
Teletext Protocol
The relationship between the TTX bit clock (6.9375 MHz) and the system CLOCK (27 MHz) for 50 Hz is given as follows: (27 MHz/4) = 6.75 MHz (6.9375 x 106/6.75 x 106 = 1.027777 Thus 37 TTX bits correspond to 144 clocks (27 MHz), each bit has a width of almost four clock cycles. The ADV7192 uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal which can be output on the CVBS and Y outputs. At the TTX input the bit duration scheme repeats after every 37 TTX bits or 144 clock cycles. The protocol requires that TTX Bits 10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. After 37 TTX bits, the next bits with three clock cycles are Bits 47, 56, 65, and 74. This scheme holds for all following cycles of 37 TTX bits, until all 360 TTX bits are completed. All teletext lines are implemented in the same way. Individual control of teletext lines are controlled by Teletext Setup Registers.
45 BYTES (360 BITS) - PAL TELETEXT VBI LINE ADDRESS & DATA
RUN-IN CLOCK
Figure 99. Teletext VBI Line
tSYNTXTOUT
CVBS/Y
tPD
HSYNC 10.2 s TTXDATA TTXDEL TTXREQ PROGRAMMABLE PULSE EDGES TTXST
tPD
tSYNTXTOUT = 10.2 s tPD = PIPELINE DELAY THROUGH ADV7192
TTXDEL = TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0-15 CLOCK CYCLES])
Figure 100. Teletext Functionality Diagram
-50-
REV. 0
ADV7192
APPENDIX 6
OPTIONAL OUTPUT FILTER
If an output filter is required for the CVBS, Y, UV, Chroma and RGB outputs of the ADV7192, the following filter in Figure 101 can be used in 2x Oversampling Mode. In 4x Oversampling Mode the filter in Figure 103 is recommended. The plot of the filter characteristics are shown in Figures 102 and 104. An output
2.5 H FILTER I/P 470pF 0.82 H FILTER O/P
filter is not required if the outputs of the ADV7192 are connected to most analog monitors or TVs, however, if the output signals are applied to a system where sampling is used, (e.g., Digital TVs) then a filter is required to prevent aliasing.
2.2 H FILTER I/P 470pF FILTER O/P
Figure 101. Output Filter for 2x Oversampling Mode
Figure 103. Output Filter for 4x Oversampling Mode
50
20
0
0
-50
AMPLITUDE - dB
1.0M 10M FREQUENCY - Hz 100M 1.0G
AMPLITUDE - dB
-20
-40
-60
-100
-80
-150 100k
-100 100k
1.0M
10M FREQUENCY - Hz
100M
1.0G
Figure 102. Output Filter Plot for 2x Oversampling Filter
Figure 104. Output Filter Plot for 4x Oversampling Filter
0
2 FILTER REQUIREMENTS
dB
4 FILTER REQUIREMENTS
-30
6.75
13.5
27.0 FREQUENCY - MHz
40.5
54.0
Figure 105. Output Filter Requirements in 4x Oversampling Mode
REV. 0
-51-
ADV7192
APPENDIX 7
DAC BUFFERING
External buffering is needed on the ADV7192 DAC outputs. The configuration in Figure 106 is recommended. When calculating absolute output full-scale current and voltage use the following equations: VOUT = IOUT x RLOAD IOUT = (VREF x K)/RSET K = 4.2146 constant, VREF = 1.235 V
VAA
+VCC 4 INPUT/ OPTIONAL FILTER O/P 5
AD8051
3 2 -VCC
1
OUTPUT TO TV MONITOR
Figure 107. Recommended DAC Output Buffer Using an Op Amp
ADV7192
VREF RSET1 1.2k DAC A DAC B DAC C PIXEL PORT DIGITAL CORE DAC D RSET2 1.2k DAC F OUTPUT BUFFER R DAC E OUTPUT BUFFER OUTPUT BUFFER OUTPUT BUFFER OUTPUT BUFFER OUTPUT BUFFER CVBS
LUMA CHROMA G B
Figure 106. Output DAC Buffering Configuration
-52-
REV. 0
ADV7192
APPENDIX 8
RECOMMENDED REGISTER VALUES
The ADV7192 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards.
NTSC (FSC = 3.5795454 MHz) Address Data Address
PAL B, D, G, H, I (FSC = 4.43361875 MHz) Data
00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 35Hex
Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Mode Register 8 Mode Register 9 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register DNR 0 DNR 1 DNR 2 Output Clock Register
10Hex 3FHex 62Hex 00Hex 00Hex 00Hex 00Hex 00Hex 04Hex 00Hex 08Hex 00Hex 16Hex 7CHex F0Hex 21Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 44Hex 20Hex 00Hex 70Hex
00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 35Hex
Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Mode Register 8 Mode Register 9 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register DNR0 DNR1 DNR2 Output Clock Register
11Hex 3FHex 62Hex 00Hex 00Hex 00Hex 00Hex 00Hex 04Hex 00Hex 08Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 44Hex 20Hex 00Hex 70Hex
REV. 0
-53-
ADV7192
PAL N (FSC = 4.43361875 MHz) Address Data Address PAL 60 (FSC = 4.43361875 MHz) Data
00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 4Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 35Hex
Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Mode Register 8 Mode Register 9 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register DNR 0 DNR 1 DNR 2 Output Clock Register
13Hex 3FHex 62Hex 00Hex 00Hex 00Hex 00Hex 00Hex 04Hex 00Hex 08Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 44Hex 20Hex 00Hex 70Hex
00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 35Hex
Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Mode Register 8 Mode Register 9 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register DNR 0 DNR 1 DNR 2 Output Clock Register
12Hex 3FHex 62Hex 00Hex 00Hex 00Hex 00Hex 00Hex 04Hex 00Hex 08Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 44Hex 20Hex 00Hex 70Hex
-54-
REV. 0
ADV7192
PAL M (FSC = 3.57561149 MHz) Address Data Address Data
00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex EHex 0FHex 10Hex 11Hex 12Hex
Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Mode Register 8 Mode Register 9 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1
12Hex 3FHex 62Hex 00Hex 00Hex 00Hex 00Hex 00Hex 04Hex 00Hex 08Hex 00Hex A3Hex EFHex E6Hex 21Hex 00Hex 00Hex 00Hex
13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 35Hex
Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register DNR 0 DNR 1 DNR 2 Output Clock Register
00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 44Hex 20Hex 00Hex 70Hex
REV. 0
-55-
ADV7192
POWER-ON RESET REGISTER VALUES POWER-ON RESET REG VALUES (PAL_NTSC = 0, NTSC Selected) Address Data Address POWER-ON RESET REG VALUES (PAL_NTSC = 1, PAL Selected) Data
00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 26Hex 27Hex 28Hex 29Hex 2AHex 2BHex 2CHex 2DHex 2EHex 2FHex 30Hex 31Hex 32Hex 33Hex 34Hex 35Hex
Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Mode Register 8 Mode Register 9 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register DNR 0 DNR 1 DNR 2 Gamma 0 Gamma 1 Gamma 2 Gamma 3 Gamma 4 Gamma 5 Gamma 6 Gamma 7 Gamma 8 Gamma 9 Gamma 10 Gamma 11 Gamma 12 Gamma 13 Brightness Detect Register Output Clock Register
00Hex 07Hex 08Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 08Hex 00Hex 16Hex 7CHex F0Hex 21Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex 72Hex
00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 26Hex 27Hex 28Hex 29Hex 2AHex 2BHex 2CHex 2DHex 2EHex 2FHex 30Hex 31Hex 32Hex 33Hex 34Hex 35Hex
Mode Register 0 Mode Register 1 Mode Register 2 Mode Register 3 Mode Register 4 Mode Register 5 Mode Register 6 Mode Register 7 Mode Register 8 Mode Register 9 Timing Register 0 Timing Register 1 Subcarrier Frequency Register 0 Subcarrier Frequency Register 1 Subcarrier Frequency Register 2 Subcarrier Frequency Register 3 Subcarrier Phase Register Closed Captioning Ext Register 0 Closed Captioning Ext Register 1 Closed Captioning Register 0 Closed Captioning Register 1 Pedestal Control Register 0 Pedestal Control Register 1 Pedestal Control Register 2 Pedestal Control Register 3 CGMS_WSS Reg 0 CGMS_WSS Reg 1 CGMS_WSS Reg 2 Teletext Control Register Contrast Control Register Color Control Register 1 Color Control Register 2 Hue Control Register Brightness Control Register Sharpness Response Register DNR 0 DNR 1 DNR 2 Gamma 0 Gamma 1 Gamma 2 Gamma 3 Gamma 4 Gamma 5 Gamma 6 Gamma 7 Gamma 8 Gamma 9 Gamma 10 Gamma 11 Gamma 12 Gamma 13 Brightness Detect Register Output Clock Register
01Hex 07Hex 08Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 08Hex 00Hex CBHex 8AHex 09Hex 2AHex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex 00Hex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex xxHex 72Hex
-56-
REV. 0
ADV7192
APPENDIX 9
NTSC WAVEFORMS (WITH PEDESTAL)
130.8 IRE
PEAK COMPOSITE
1268.1mV
100 IRE
REF WHITE
1048.4mV
714.2mV 7.5 IRE 0 IRE -40 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.6mV 334.2mV 48.3mV
Figure 108. NTSC Composite Video Levels
100 IRE
REF WHITE
1048.4mV
714.2mV 7.5 IRE 0 IRE -40 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.6mV 334.2mV 48.3mV
Figure 109. NTSC Luma Video Levels
1067.7mV 835mV (pk-pk)
PEAK CHROMA
286mV (pk-pk) 650mV
BLANK/BLACK LEVEL
232.2mV
PEAK CHROMA
0mV
Figure 110. NTSC Chroma Video Levels
100 IRE
REF WHITE
1052.2mV
720.8mV 7.5 IRE 0 IRE -40 IRE BLACK LEVEL BLANK LEVEL SYNC LEVEL 387.5mV 331.4mV 45.9mV
Figure 111. NTSC RGB Video Levels
REV. 0
-57-
ADV7192
NTSC WAVEFORMS (WITHOUT PEDESTAL)
130.8 IRE
PEAK COMPOSITE
1289.8mV
100 IRE
REF WHITE
1052.2mV
714.2mV 0 IRE -40 IRE BLANK/BLACK LEVEL SYNC LEVEL 338mV 52.1mV
Figure 112. NTSC Composite Video Levels
100 IRE
REF WHITE
1052.2mV
714.2mV
0 IRE -40 IRE
BLANK/BLACK LEVEL SYNC LEVEL
338mV 52.1mV
Figure 113. NTSC Luma Video Levels
1101.6mV 903.2mV (pk-pk)
PEAK CHROMA
307mV (pk-pk) 650mV
BLANK/BLACK LEVEL
198.4mV
PEAK CHROMA
0mV
Figure 114. NTSC Chroma Video Levels
100 IRE
REF WHITE
1052.2mV
715.7mV
0 IRE -40 IRE
BLANK/BLACK LEVEL SYNC LEVEL
336.5mV 51mV
Figure 115. NTSC RGB Video Levels
-58-
REV. 0
ADV7192
PAL WAVEFORMS
1284.2mV
PEAK COMPOSITE
1047.1mV
REF WHITE
696.4mV 350.7mV 50.8mV BLANK/BLACK LEVEL SYNC LEVEL
Figure 116. PAL Composite Video Levels
1047mV
REF WHITE
696.4mV
350.7mV 50.8mV
BLANK/BLACK LEVEL SYNC LEVEL
Figure 117. PAL Luma Video Levels
1092.5mV 885mV (pk-pk)
PEAK CHROMA
300mV (pk-pk) 650mV
BLANK/BLACK LEVEL
207.5mV
PEAK CHROMA
0mV
Figure 118. PAL Chroma Video Levels
1050.2mV
REF WHITE
698.4mV
351.8mV 51mV
BLANK/BLACK LEVEL SYNC LEVEL
Figure 119. PAL RGB Video Levels
REV. 0
-59-
ADV7192
VIDEO MEASUREMENT PLOTS
COLOR BAR (NTSC) FIELD = 1 LINE = 21 LUMINANCE LEVEL (IRE) 99.6 100 50 0 GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK 69.0 55.9 48.1 36.3 28.3 15.7 7.7 WFM FCC COLOR BAR
CHROMINANCE LEVEL (IRE) 0.0 100 50 0 GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK 62.1 87.6 81.8 81.8 87.8 62.1 0.0
CHROMINANCE PHASE (DEGREE) 167.3 400 200 0 GRAY AVERAGE 32 YELLOW 32 CYAN GREEN MAGENTA RED BLUE BLACK 283.8 240.9 60.80 103.6 347.1
Figure 120. NTSC Color Bar Measurement
COLOR BAR (PAL) FIELD = 1 LINE = 21 LUMINANCE LEVEL (mV) 1000 695.7 464.8 366.6 305.7 217.3 156.4 61.2 -0.4 WFM FCC COLOR BAR
500
0 GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK
CHROMINANCE LEVEL (mV) 1000 0.0 474.4 669.1 623.5 624.7 669.6 475.2 0.0
500
0 GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK
CHROMINANCE PHASE (DEGREE) 166.7 400 300 200 100 0 GRAY AVERAGE 32 YELLOW 32 CYAN GREEN MAGENTA RED BLUE BLACK 283.3 240.4 60.4 103.2 346.7
Figure 121. PAL Color Bar Measurement
-60-
REV. 0
ADV7192
DG DP (NTSC) FIELD = 1, LINE = 21 DIIFFERENTIAL GAIN (PERCENT) 2.5 1.5 0.5 -0.5 -1.5 -2.5 1st 2nd 3rd 4th 5th 6th 0.00 0.21 0.02 MIN = 0.00, MAX = 0.27, p-p/MAX = 0.27 0.07 0.27 0.08 2.5 1.5 0.5 -0.5 -1.5 -2.5 1st 2nd 3rd 4th 5th 6th WFM MOD 5 STEP DG DP (PAL) LINE = 570 DIIFFERENTIAL GAIN (PERCENT) 0.00 0.30 0.15 MIN = 0.00, MAX = 0.32, p-p/MAX = 0.32 0.24 0.32 0.26 WFM MOD 5 STEP
DIFFERENTIAL PHASE (DEGREE) 2.5 1.5 0.5 -0.5 -1.5 -2.5 1st AVERAGE 32 2nd 32 3rd 0.00 0.10 0.12
MIN = 0.00, MAX = 0.20, p-p = 0.20 0.15 0.13 0.10 2.5 1.5 0.5 -0.5 -1.5 4th 5th 6th -2.5
DIFFERENTIAL PHASE (DEGREE) 0.00 0.09 0.13
MIN = 0.00, MAX = 0.16, p-p = 0.16 0.16 0.12 0.14
1st AVERAGE 32
2nd 32
3rd
4th
5th
6th
Figure 122. NTSC DG DP Measurement
Figure 124. PAL DG DP Measurement
LUMINANCE NONLINEARITY (NTSC) FIELD = 2, LINE = 77 LUMINANCE NONLINEARITY (PERCENT) 111 109 107 105 103 101 99 97 95 93 99.9 99.9 99.6
WFM
MOD 5 STEP p-p = 0.4 100.0 99.9
LUMINANCE NONLINEARITY (PAL) LINE = 570 LUMINANCE NONLINEARITY (PERCENT) 113 111 109 107 105 103 101 99 97 95 99.6 99.9 100.0
WFM
MOD 5 STEP p-p = 0.8 99.6 99.9
91
93
89 1st AVERAGE 32 2nd 32 3rd 4th 5th
91 1st AVERAGE 32 32 2nd 3rd 4th 5th
Figure 123. NTSC Luminance Nonlinearity
Figure 125. PAL Luminance Nonlinearity
REV. 0
-61-
ADV7192
CHROMINANCE NONLINEARITY(NTSC) WFM FIELD = 2, LINE = 217 CHROMINANCE AMPLITUDE ERROR (PERCENT) 0.5 10 0 -10 20IRE 40IRE 80IRE REF = 40IRE PACKET 0.0 0.0 NTSC-7 COMBINATION REF = 40IRE PACKET -0.3 10 0 -10 140mV 420mV 700mV REF = 420mV PACKET -0.3 CHROMINANCE NONLINEARITY(PAL) WFM LINE = 572 CHROMINANCE AMPLITUDE ERROR (PERCENT) 0.6 0.0 MOD 3 STEP REF = 420mV PACKET -0.4
CHROMINANCE PHASE ERROR (DEGREE) 5 -0.0 0.0
CHROMINANCE PHASE ERROR (DEGREE) -0.3 0.0
0 -5 20IRE 40IRE 80IRE
0
-5 140mV 420mV 700mV
CHROMINANCE LUMINANCE INTERMODULATION (PERCENT OF 714 mV) 0.0 0.2 0.1 0.0 -0.1 -0.2 20IRE AVERAGE 32 32 40IRE 80IRE -0.2 0.2 0.0 0.1 0.1
CHROMINANCE LUMINANCE INTERMODULATION (PERCENT OF 700mV) 0.0 0.0 0.1
140mV AVERAGE 32 32
420mV
700mV
Figure 126. NTSC Chrominance Nonlinearity
Figure 128. PAL Chrominance Nonlinearity
CHROMINANCE AM/PM (NTSC) FIELD = 2, LINE = 217 BANDWIDTH 10kHz TO 100kHz AM NOISE
WFM
RED FIELD
CHROMINANCE AM/PM (PAL) LINE = 572 BANDWIDTH 10kHz TO 100kHz
WFM
APPROPRIATE
-86.5dB RMS
AM NOISE
-84.2dB RMS
-95
-90
-85
-80
-75
-70
-65
-60 dB RMS
-95
-90
-85
-80
-75
-70
-65
-60 dB RMS
PM NOISE
-82.7dB RMS
PM NOISE
-82.7dB RMS
-95
-90
-85
-80
-75
-70
-65
-60 dB RMS
-95
-90
-85
-80
-75
-70
-65
-60 dB RMS
(0dB = 714mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL)
(0dB = 700mV p-p WITH AGC FOR 100% CHROMINANCE LEVEL)
Figure 127. NTSC Chrominance AM/PM
Figure 129. PAL Chrominance AM/PM
-62-
REV. 0
ADV7192
NOISE SPECTRUM (NTSC) FIELD = 2, LINE = 223 AMPLITUDE (0dB = 714mV p-p) BANDWIDTH 10kHz TO FULL 20 0 NOISE LEVEL = -79.7dB RMS WFM PEDESTAL NOISE SPECTRUM (PAL) LINE = 511 AMPLITUDE (0dB = 714mV p-p) BANDWIDTH 10kHz TO FULL NOISE LEVEL = -79.1dB RMS WFM PEDESTAL
0 -20 -20 -40 -40 -60 -60 -80
-80
-100 1 2 3 MHz 4 5 6
-100 1 2 3 MHz 4 5 6 7
Figure 130. NTSC Noise Spectrum: Pedestal
Figure 132. PAL Noise Spectrum: Pedestal
NOISE SPECTRUM (NTSC) FIELD = 2, LINE = 217 AMPLITUDE (0dB = 714mV p-p) BANDWIDTH 100kHz TO FULL (TILT NULL) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1 2 3 MHz
WFM
RAMP
NOISE SPECTRUM (PAL) LINE = 572 AMPLITUDE (0dB = 700mV P-P) BANDWIDTH 100kHz TO FULL (TILT NULL) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
WFM
RAMP
NOISE LEVEL = -63.1dB RMS
NOISE LEVEL = -62.3dB RMS
4
5
6
1
2
3 MHz
4
5
6
7
Figure 131. NTSC Noise Spectrum: Ramp
Figure 133. PAL Noise Spectrum: Ramp
REV. 0
-63-
ADV7192
UV WAVEFORMS
MAGENTA
MAGENTA YELLOW
YELLOW
GREEN
GREEN
BLACK
WHITE
CYAN
BLUE
RED
505mV
423mV
505mV
334mV
171mV BETACAM LEVEL 0mV 0mV
BETACAM LEVEL 82mV 0mV -82mV 0mV
171mV
334mV
-423mV
505mV
-505mV
Figure 134. NTSC 100% Color Bars No Pedestal U Levels
Figure 137. NTSC 100% Color Bars No Pedestal V Levels
MAGENTA
MAGENTA
YELLOW
YELLOW
GREEN
GREEN
BLACK
467mV
467mV 391mV
309mV
158mV BETACAM LEVEL 0mV 0mV
BETACAM LEVEL 76mV 0mV -76mV
-158mV
BLACK
WHITE
WHITE
CYAN
CYAN
BLUE
BLUE
RED
RED
BLACK
WHITE
CYAN
BLUE
RED
0mV
-309mV
-391mV
-467mV
-467mV
Figure 135. NTSC 100% Color Bars with Pedestal U Levels
Figure 138. NTSC 100% Color Bars with Pedestal V
MAGENTA
MAGENTA
YELLOW
YELLOW
GREEN
GREEN
BLACK
350mV 293mV 232mV SMPTE LEVEL 118mV SMPTE LEVEL 57mV 0mV 0mV 0mV
350mV
BLACK 0mV
WHITE
WHITE
CYAN
CYAN
BLUE
-57mV -118mV -232mV -293mV -350mV -350mV
Figure 136. PAL 100% Color Bars U Levels
Figure 139. PAL 100% Color Bars V Levels
BLUE
RED
RED
-64-
REV. 0
ADV7192
OUTPUT WAVEFORMS
0.6
0.4
VOLTS
0.2
0.0
0.2 L608
0.0
10.0
20.0
30.0 MICROSECONDS
40.0
50.0
60.0
NOISE REDUCTION: 0.00 dB APL = 39.1% 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s
PRECISION MODE OFF SYNCHRONOUS
SOUND-IN-SYNC OFF SYNC = SOURCE
FRAMES SELECTED: 1 2 3 4
Figure 140. 100%/75% PAL Color Bars
0.5
VOLTS
0.0
L575
0.0
10.0
20.0
APL NEEDS SYNC = SOURCE! 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s
30.0 40.0 50.0 60.0 70.0 NO BRUCH SIGNAL MICROSECONDS PRECISION MODE OFF SOUND-IN-SYNC OFF SYNCHRONOUS SYNC = A FRAMES SELECTED: 1
Figure 141. 100%/75% PAL Color Bars Luminance
REV. 0
-65-
ADV7192
0.5
VOLTS
0.0
-0.5 L575
10.0
20.0
30.0
40.0
50.0 NO BRUCH SIGNAL
60.0 SOUND-IN-SYNC OFF SYNC = A
MICROSECONDS APL NEEDS SYNC = SOURCE! 625 LINE PAL NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s
PRECISION MODE OFF SYNCHRONOUS
FRAMES SELECTED: 1
Figure 142. 100%/75% PAL Color Bars Chrominance
100.0
0.5
IRE:FLT
0.0
VOLTS
50.0
0.0
-50.0
F1 L76
0.0 APL = 44.6% 525 LINE NTSC
10.0
20.0
30.0 40.0 MICROSECONDS PRECISION MODE OFF
50.0
60.0
NO FILTERING
SYNCHRONOUS
SYNC = A
SLOW CLAMP TO 0.00 V AT 6.72 s
FRAMES SELECTED: 1 2
Figure 143. 100%/75% NTSC Color Bars
-66-
REV. 0
ADV7192
100.0 0.6
0.4
IRE:FLT VOLTS
50.0
0.2
0.0
0.0
-0.2 F2 L238
10.0
20.0
30.0 40.0 MICROSECONDS
50.0
60.0
NOISE REDUCTION: 15.05dB APL = 44.7% 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s
PRECISION MODE OFF SYNCHRONOUS
SYNC = SOURCE
FRAMES SELECTED: 1 2
Figure 144. 100%/75% NTSC Color Bars Luminance
0.4 50.0
0.2
IRE:FLT VOLTS
0.0
-0.2
-50.0 -0.4 F1 L76
0.0
10.0
20.0
30.0 40.0 MICROSECONDS PRECISION MODE OFF
50.0
60.0
NOISE REDUCTION: 15.05dB APL NEEDS SYNC = SOURCE! 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0.00 V AT 6.72 s
SYNCHRONOUS
SYNC = B
FRAMES SELECTED: 1 2
Figure 145. NTSC Color Bars Chrominance
REV. 0
-67-
ADV7192
APPENDIX 10
VECTOR PLOTS
V APL = 39.6% cy SYSTEM LINE L608 ANGLE (DEG) 0.0 GAIN 1.000 0.000dB 625 LINE PAL BURST FROM SOURCE DISPLAY +V AND -V M g
g
R
75% 100% YI b U
yl
B
G Cy m g
r
SOUND IN SYNC OFF
Figure 146. PAL Vector Plot
R-Y APL = 45.1% I cy SYSTEM LINE L76F1 ANGLE (DEG) 0.0 GAIN 1.000 0.000dB 525 LINE NTSC BURST FROM SOURCE
R M g Q
YI 100%
b B-Y
75% B
G Cy -Q
-I
SETUP 7.5%
Figure 147. NTSC Vector Plot
-68-
REV. 0
ADV7192
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
80-Lead LQFP (ST-80)
0.640 (16.25) SQ 0.620 (15.75) 0.553 (14.05) SQ 0.549 (13.95)
80 1 61 60
0.063 (1.60) MAX 0.030 (0.75) 0.020 (0.50) SEATING PLANE
TOP VIEW
(PINS DOWN)
0.486 (12.35) TYP SQ
0.004 (0.10) MAX 0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.35)
20 21
41 40
0.029 (0.73) 0.022 (0.57)
0.014 (0.35) 0.010 (0.25)
REV. 0
-69-
PRINTED IN U.S.A.
C3748-8-4/00 (rev. 0) 00229

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